PDF TEF6730 Data sheet ( Hoja de datos )

Número de pieza	TEF6730
Descripción	Front-end for digital-IF car radio
Fabricantes	NXP Semiconductors
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No Preview Available ! TEF6730 Front-end for digital-IF car radio Rev. 01 — 10 July 2006 Product data sheet 1. General description www.DataSheet4U.com The TEF6730 is a car radio tuner front-end for digital-IF reception, especially designed for co-operation with digital-IF DSP back-ends of the SAF773x and SAF778x families. The FM tuner features single conversion to IF = 10.7 MHz and integrated image rejection; capable for FM 65 MHz to 108 MHz and weather band reception. The AM tuner features single conversion to IF = 10.7 MHz with an integrated AM front-end, capable for LW, MW and full SW reception. A combined AM/FM IF AGC ampliﬁer provides a suitable IF signal to the ADC in IF DSP. The device can be controlled via the fast-mode I2C-bus (400 kHz) and includes autonomous tuning functions for easy control. No manual alignments are required. 2. Features I FM mixer for conversion of FM RF to IF 10.7 MHz with large dynamic range, high image rejection and selectable mixer gain I Selectable high or low injection of LO I AGC PIN diode drive circuit for FM RF AGC with detection at RF and IF, including keyed AGC function I RF input for weather band applications I Integrated AM front-end LNA I Integrated AM RF AGC for low desensitization and AGC PIN diode drive circuit with detection at RF and IF I AM mixer for conversion of AM RF to IF 10.7 MHz I AM/FM IF AGC ampliﬁer with large dynamic range, gain controlled from IF DSP I AM and FM front-end AGC information is available via the I2C-bus I Low phase noise local oscillator with reliable start-up behavior I In-lock detection for optimized adaptive PLL tuning speed I Programmable divider and mixer dividers for reception of FM (65 MHz to 108 MHz), weather band, AM LW, MW and full SW I Two antenna DAAs I Sequential state machine supporting all tuning actions including AFU for RDS I Interfacing signals for IF AGC, FM keyed AGC, AFU and reference frequency to IF DSP for optimum system performance I Software controlled ﬂag outputs I Selection of four I2C-bus addresses 1 page xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x 40 OSCTNK 39 OSCFDB CPOUT VTUNE 36 35 DAAOUT2 DAAOUT1 WXMIXDEC WXMIXIN 33 32 29 28 FMMIXIN2 FMMIXIN1 27 26 30 IFMAGC 37 pll 38 vco 41 vco 53 54 PLL REF ÷N fref Φ 55 vref BAND ÷M 56 sup 57 sup 45 fgnd 52 dig 16, 18, 48, 49 i.c. flag 42 SWPORT pll in-lock TUNING STATE MACHINE 43 AFSAMPLE 44 AFHOLD antenna DAA MIXER 90° WX TEF6730HW tuner control CTRL BUF 46 address 47 write I2C-BUS 50 read 51 ADDR2 ADDR1 SDA SCL ifagc MIXER 90° FM ifagc MIXER FM RF AGC rf AM RF AGC AM LNA lna lna rf am/fm rf agc IF AGC 58 59 60 61 ifagc IFOUT1 IFOUT2 IFAGCMSB IFAGCLSB 34 31 25 24 23 22 21 20 19 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 Fig 1. Block diagram of TEF6730HW 001aae088 5 Page Philips Semiconductors TEF6730 Front-end for digital-IF car radio www.DataSheet4U.com Table 7. Bit 7 and 6 5 and 4 3 to 1 0 TUNER - data byte 0h bit description Symbol Description RAGC[1:0] RF AGC attenuation indicator, PIN diode current on pin IFMAGC AM mode: 00 = no AGC 01 = LNA AGC 10 = IAGC < 1 mA 11 = IAGC > 1 mA FM mode: 00 = < 0.1 mA 01 = 0.1 mA to 0.5 mA 10 = 0.5 mA to 2.5 mA 11 = > 2.5 mA TAS[1:0] tuning action state; the signal TAS informs about internal control functions of the tuner action state machine; this way the progress of tuner actions can be monitored by the microcontroller; see Figure 8 to Figure 18 00 = no current action 01 = mute started and in progress at DSP 10 = PLL tuning in progress and mute activated at DSP 11 = PLL tuning ready and mute activated at DSP - not used POR power-on reset 0 = normal operation 1 = I2C-bus data is reset to default POR state; POR is reset to logic 0 after the TEF6730 has been read out and written to via I2C-bus at least once 8.1.2 Read mode: data byte ID Table 8. 7 - ID - data byte 1h bit allocation 654 --- 3210 - ID2 ID1 ID0 Table 9. Bit 7 to 3 2 to 0 ID - data byte 1h bit description Symbol Description - not used ID[2:0] device type identiﬁcation 110 = TEF6730 8.2 Write mode The tuner is controlled by the I2C-bus. After the IC address the MSA byte contains the control of the tuning action via the bits MODE[2:0] and REGC and subaddressing via bits SA[3:0] (see Figure 5). TEF6730_1 Product data sheet Rev. 01 — 10 July 2006 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. 11 of 56 11 Page

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