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PDF TDA9917 Data sheet ( Hoja de datos )
| Número de pieza | TDA9917 | |
| Descripción | up to 250 Msample/s Analog-to-Digital Converter (ADC) | |
| Fabricantes | NXP Semiconductors | |
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TDA9917
8-bit, up to 250 Msample/s Analog-to-Digital Converter (ADC)
Rev. 01 — 9 June 2006
Objective data sheet
1. General description
www.DataSheet4U.com
The TDA9917 is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC)
optimized for telecommunication transmission control systems and tape drive
applications.
The TDA9917 offers the selection between Low-Voltage Differential Signals (LVDS) and
1.8 V Complementary Metal Oxide Semiconductor (CMOS) levels interface for the clock.
The output data interface is 1.8 V CMOS levels. It allows to sample the signal up to
250 Msample/s. All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and
DEL1) are 1.8 V CMOS compatible. The TDA9917 offers the most possible flexible
acquisition control system thanks to its programmable Complete Conversion Signal (CCS)
that allows to adjust the delay of the acquisition clock and its frequency.
The TDA9917 is released in HTQFP48 package.
2. Features
I 8-bit resolution
I High-speed sampling rate up to 250 Msample/s
I Maximum analog input frequency up to 450 MHz
I Programmable acquisition output clock (complete conversion signal)
I Differential analog input
I Integrated voltage regulator or external control for analog input full-scale
I Integrated voltage regulator for input common-mode reference
I Selectable 1.8 V CMOS or LVDS clock input
I 1.8 V CMOS digital outputs
I 1.8 V CMOS compatible static digital inputs
I Binary or two’s complement CMOS outputs
I Only 2 clock cycles latency
I Industrial temperature range from −40 °C to +85 °C
I HTQFP48 package
3. Applications
I 2.5G and 3G cellular base infrastructure radio transceivers
I Wireless access systems
I Fixed telecommunication
I Optical networking
I Wireless Local Area Network (WLAN) infrastructure
1 page  
Philips Semiconductors
TDA9917
8-bit, up to 250 Msample/s Analog-to-Digital Converter (ADC)
Table 3. Pin type description …continued
Type
Description
O(CMOS)
1.8 V CMOS level output
P power supply
G ground
7. Limiting values
www.DataSheet4U.com
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VCCA
VCCD
VCCO
∆VCC
Vi(IN)
Vi(INN)
Vi(clk)(p-p)
analog supply voltage
digital supply voltage
output supply voltage
supply voltage difference
VCCA − VCCD
VCCD − VCCO
VCCA − VCCO
input voltage on pin IN
input voltage on pin INN
peak-to-peak clock input
voltage
[1] <tbd>
[1] <tbd>
[2] <tbd>
referenced to AGND
referenced to AGND
referenced to DGND
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
IO
Tstg
Tamb
Tj
output current
storage temperature
ambient temperature
junction temperature
<tbd>
−55
−40
-
Max
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
+150
+85
150
Unit
V
V
V
V
V
V
V
V
V
mA
°C
°C
°C
[1] The supply voltages VCCA and VCCD may have any value between −0.5 V and +7.0 V provided that the
supply voltage differences ∆VCC are respected.
[2] The supply voltage VCCO may have any value between −0.5 V and +5.0 V provided that the supply voltage
differences ∆VCC are respected.
8. Thermal characteristics
Table 5.
Symbol
Rth(j-a)
Rth(c-a)
Thermal characteristics
Parameter
thermal resistance from junction to ambient
thermal resistance from case to ambient
Conditions
in free air
in free air
Typ
<tbd>
<tbd>
Unit
K/W
K/W
TDA9917_1
Objective data sheet
Rev. 01 — 9 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 20
5 Page 
Philips Semiconductors
TDA9917
8-bit, up to 250 Msample/s Analog-to-Digital Converter (ADC)
www.DataSheet4U.com
The TDA9917 generates an adjustable clock output called Complete Conversion Signal
(CCS), which can be used to control the acquisition of converted output data by the digital
circuit connected to the TDA9917 output data bus.
Two logic input pins DEL0 and DEL1 allow to adjust the delay of the edge of the CCS
signal to achieve an optimal position in the stable, usable zone of the data. Pin CLKSEL
allows the selection of the CCS frequency; see Table 13.
Table 13. Complete conversion signal frequency selection
Control input for CCS frequency selection
(pin CCSSEL)
CCS frequency (fCCS)
HIGH or not connected
fclk
LOW
fclk/2
D0 to D7
CCS (fclk)
data
n−2
data
n−1
tcd(o)
data
n
data
n+1
50 %
CCS (fclk/2)
50 %
001aab893
Fig 4. Complete conversion signal timing diagram, standard mode
11. Definitions
11.1 Static parameters
11.1.1 INL (integral non-linearity)
It is defined as the deviation of the transfer function from a best fit straight line (linear
regression computation). The INL of the code i is obtained from the equation:
INL(i) = -V----I--(--i--)----–----V-----I--(--i--d----e---a---l--)-
S
where:
S = corresponding to the slope of the ideal straight line (code width)
i = corresponding to the code value.
11.1.2 DNL (differential non-linearity)
It is the deviation in code width from the value of 1 LSB.
TDA9917_1
Objective data sheet
Rev. 01 — 9 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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