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PDF PCK9456 Data sheet ( Hoja de datos )

Número de pieza PCK9456
Descripción 2.5 V and 3.3 V LVCMOS clock fan-out buffer
Fabricantes NXP Semiconductors 
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No Preview Available ! PCK9456 Hoja de datos, Descripción, Manual

PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
Rev. 01 — 31 July 2006
Product data sheet
1. General description
www.DataSheet4U.com
2. Features
The PCK9456 is a 2.5 V and 3.3 V compatible 1 : 10 clock distribution buffer designed for
low voltage mid-range to high-performance telecommunications, networking and
computing applications. Both 3.3 V, 2.5 V and dual supply voltages are supported for
mixed voltage applications. The PCK9456 offers 10 low-skew outputs and a differential
LVPECL clock input. The outputs are configurable and support 1 : 1 and 1 : 2 output to
input frequency ratios. The PCK9456 is specified for the extended temperature range of
40 °C to +85 °C.
I Configurable 10 outputs LVCMOS clock distribution buffer
I Compatible to single, dual and mixed 3.3 V/2.5 V voltage supply
I Wide range output clock frequency up to 250 MHz
I Designed for mid-range to high performance telecommunications, networking and
computer applications
I Supports high performance differential clocking applications
I Maximum output skew of 200 ps (150 ps within one bank)
I Selectable output configurations per output bank
I 3-stateable outputs
I Available in LQFP32 package
I Ambient operating temperature of 40 °C to +85 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description
PCK9456BD
LQFP32 plastic low profile quad flat package; 32 leads;
body 7 × 7 × 1.4 mm
Version
SOT358-1

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PCK9456 pdf
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
7. Limiting values
www.DataSheet4U.com
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
VCC supply voltage
VI input voltage
VO output voltage
0.3
0.3
0.3
II input current
IO output current
Tstg storage temperature
-
-
40
8. Recommended operating conditions
Max
+4.6
VCC + 0.3
VCC + 0.3
±20
±50
+125
Unit
V
V
V
mA
mA
°C
Table 6. Operating conditions
Symbol Parameter
VCC
VCC(bankA)
VCC(bankB)
VCC(bankC)
Tamb
supply voltage
supply voltage (bank A)
supply voltage (bank B)
supply voltage (bank C)
ambient temperature
Conditions
VCCA pins
VCCB pins
VCCC pins
Min
2.375
2.375
2.375
2.375
40
Typ
-
-
-
-
-
Max
3.465
3.465
3.465
3.465
+85
Unit
V
V
V
V
°C
9. Characteristics
Table 7.
Symbol
VT
Vesd
General characteristics
Parameter
termination voltage
electrostatic discharge
voltage
Ilatch(prot)
CPD
Ci
latch-up protection current
power dissipation
capacitance
input capacitance
Conditions
output
MM
HBM
per output
Min
-
200
2000
200
-
-
Typ
0.5VCC
-
-
-
10
Max
-
-
-
-
-
Unit
V
V
V
mA
pF
4.0 -
pF
PCK9456_1
Product data sheet
Rev. 01 — 31 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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PCK9456 arduino
Philips Semiconductors
PCK9456
2.5 V and 3.3 V LVCMOS clock fan-out buffer
www.DataSheet4U.com
The waveform plots of Figure 8 show simulation results of an output driving a single line
versus two lines. In both cases the drive capability of the PCK9456 output buffer is more
than sufficient to drive 50 transmission lines on the incident edge. Note from the delay
measurement in the simulations a delta of only 43 ps exists between the two differently
loaded outputs. This suggests that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the PCK9456. The output waveform in Figure 8
shows a step in the waveform; this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36 series resistor plus the output
impedance does not match the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL
=
V
S
-R---s----+-----RZ----oo---+-----Z----o-
where:
Zo = 50 Ω || 50
Rs = 36 Ω || 36
Ro = 14
VL
=
3.0
1----8----+-----12---45----+-----2---5--
=
1.31
V
At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5 V.
It will then increment towards the quiescent 3.0 V in steps separated by one round trip
delay (in this case 4.0 ns).
3.0
voltage
(V)
2.0
IN
1.0
002aab874
OutA
td = 3.8956 ns
OutB
td = 3.9386 ns
PCK9456_1
Product data sheet
0
0.5
0 4 8 12 16
time (ns)
Fig 8. Single versus dual line termination waveforms
Since this step is well above the threshold region it will not cause any false clock
triggering, however designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure 9
should be used. In this case the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance the line impedance is
perfectly matched.
Rev. 01 — 31 July 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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