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PDF EMD28164PA Data sheet ( Hoja de datos )

Número de pieza EMD28164PA
Descripción 8M x 16 Mobile DDR SDRAM
Fabricantes Emerging Memory & Logic Solutions 
Logotipo Emerging Memory & Logic Solutions Logotipo



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No Preview Available ! EMD28164PA Hoja de datos, Descripción, Manual

Document Title
128M: 8M x 16 Mobile DDR SDRAM
EMD28164PA
128M: 8M x 16 Mobile DDR SDRAM
Revision History
Revision No.
0.0
0.1
Date
Jun 4, 2007
Nov 8, 2007
www.DataSheet4U.com
1.0 May 26, 2008
History
Initial Draft
- Table 8 Operating AC Parameter updated for tCKE and tWR
- Table 2 Bonding Pad Location and Identification Table deleted
- Signal names unified to /CK, /CS, /RAS, /CAS, /WE respectively
(Ex.) CK#, CK, CKB unified to /CK
- Corrected IDD6 value in Table 16
Release
- Table 6 DC CHARACTERISTICS updated for IDD3P, IDD3N, IDD6
- Table 8 OPERATING AC PARAMETER updated for tDS, tDH, tQH, tRC
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperation B/D, 301-1 Yeon-Dong, Jeju-Do, Korea Zip Code : 690-717
Tel : +82-64-740-1700 Fax : +82-64-740-1750 / Homepage : www.emlsi.com
The attached datasheets provided by EMLSI reserve the right to change the specifications and products.
EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI
office.
1 Rev 1.0

1 page




EMD28164PA pdf
FUNCTIONAL BLOCK DIAGRAM
EMD28164PA
128M: 8M x 16 Mobile DDR SDRAM
REFRESH
COUNTER
12
ROW -
ADDRESS 4,096
DECODER
www.DataSheet4U.com
12
x4
A0 - A11
BA0, BA1
14
2
BANK
2 CONTROL
LOGIC
8
CKE
CK
/CK
/CS
/RAS
/CAS
/WE
14
CONTROL
LOGIC
COMMAND
DECODE
STANDARD MODE
REGISTER
EXTENDED MODE
REGISTER
BANK
MEMORY
ARRAY
(4,096 x 256 x 32)
x4
SENSE AMPLIFIERS
DQS
GENERATOR
2
DQS
DRIVER
2
Dout
32
Parallel
to
16
Dout
DRIVER
16
Serial
256 32
COLUMN -
ADDRESS
DECODERx 4
I/O GATING
DM MASK LOGIC
32
32
Din
Serial
to
Parallel
16 Din
INPUT BUF.
1
2
2
DQS
INPUT BUF.
DM
INPUT BUF.
16
2
2
DQ0 -
DQ15
LDQS
UDQS
LDM
UDM
5 Rev 1.0

5 Page





EMD28164PA arduino
EMD28164PA
128M: 8M x 16 Mobile DDR SDRAM
Table 10: I/O Setup/Hold Slew Rate
I/O Setup/Hold Slew Rate
(V/ns)
1.0
0.8
0.6
tDS
(ps)
0
+75
+150
4. This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns.
tDH
(ps)
0
+75
+150
Table 11: I/O Delta Rise/Fall Rate(1/slewrate)
Delta Rise/Fall Rate
(ns/V)
www.DataSheet4U.com 0
0.25
0.5
tDS
(ps)
0
+50
+100
tDH
(ps)
0
+50
+100
5. This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as
1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 = 0.8V/ns, then the Delta Rise/Fall Rate = -0.25ns/V.
6. Maximum burst refresh cycle : 8
11 Rev 1.0

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