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PDF PAS5101PE Data sheet ( Hoja de datos )
| Número de pieza | PAS5101PE | |
| Descripción | CMOS 1.3MEGA DIGITAL IMAGE SESNSOR | |
| Fabricantes | Pixart Imaging | |
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PAS5101PE Specification
PAS5101PE CMOS 1.3MEGA DIGITAL IMAGE SESNSOR
General Description
The PAS5101PE is a highly integrated CMOS active-pixel image sensor that has resolution of 1280( H ) x
1024 ( V ). To have an excellent image quality, the PAS5101PE output 10-bits RGB raw data though a parallel
data bus. It is available in 48-pin LCC.
The PAS5101PE can be programmed to set the exposure time for different luminance condition via I2CTM
serial control bus. By programming the internal register sets, it performs on-chip frame rate adjustment, offset
correction DAC, programmable gain control, 10-bits ADC, 10-bits output companding, interpolated sub-
sampling and defect compensation.
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Features
Key Specification
z 1.3Mega resolution, ~1/3” Lens.
Supply Voltage
2.5v ~ 3.3v
z Bayer RGB color filter array.
z 10-bits parallel RGB raw data output.
z On-Chip 10-bits pipeline A/D converter.
z On-Chip programmable gain amplifier
Resolution
Array Diagonal
Pixel Size
1280 ( H ) x 1024 ( V )
5.9mm ( ~1/3” Optic )
3.6μm x 3.6μm
4-bits color gain amplifier.
Max. Frame Rate
~15 fps @ 1.3Mega
4-bits global gain amplifier.
z Digital gain stage.
z Continuous variable frame time.
z Continuous variable exposure time.
Max. System Clock
Max. Pixel Clock
Color Filter
Up to 48MHz
Up to 24MHz
RGB Bayer Pattern
z I2CTM interface.
Exposure Time
~ Frame time to Line time
z 20mA power dissipation ( 15fps / 2.5v ).
z < 10uA low power-down dissipation.
z Window-of-Interest (WOI).
z Sub-sampling.
Scan Mode
Sensitivity
S/N Ratio
Progressive
TBD
TBD
z Defect compensation.
Chief Ray Angle
20° ~ 24°
z Lens shading compensation.
Package Type
48-pin LCC
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
1
PixArt Imaging Inc.
E-mail: [email protected]
v1.0 2005/4/27
1 page  
PAS5101PE Specification
www.DataSheet4U.com
Figure 2.3 Inter-frame timing
Figure 2.4 Inter-frame timing @ Dark masked
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
5
PixArt Imaging Inc.
E-mail: [email protected]
v1.0 2005/4/27
5 Page 
PAS5101PE Specification
4. I2CTM Bus
PAS5101PE supports I2C bus transfer protocol and is acting as slave device. The 7 bits unique slave
address is “1000000” and supports receiving / transmitting speed up to 400KHz.
4.1. I2C Bus Overview
z Only two wires SDA ( serial data ) and SCL ( serial clock ) carry information between the
devices connected to the I2C bus. Normally both SDA and SCL lines are open collector
structure and pull high by external pull-up resistors.
z Only the master can initiates a transfer ( start ), generates clock signals, and terminates a
transfer ( stop ).
www.DataSheet4U.czom Start and stop condition : A high to low transition of the SDA line while SCA is high defines
a start condition. A low to high transition of the SDA line while SCA is high defines a stop
condition. Please refer to Figure 4.1.
z Valid data : The data on the SDA line must be stable during the high period of the SCA clock.
Within each byte, MSB is always transferred first. Read / Write control bit is the LSB of the
first byte. Please refer to Figure 4.2.
z Both the master and slave can transmit and receive data from the bus.
z Acknowledge : The receiving device should pull down the SDA line during high period of the
SCL clock line when a complete byte was transferred by transmitter. In the case of a master
received data from a slave, the master does not generate an acknowledgment on the last byte
to indicate the end of a master read cycle.
Figure 4.1 Start and Stop conditions
Figure 4.2 Valid Data
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11
PixArt Imaging Inc.
E-mail: [email protected]
v1.0 2005/4/27
11 Page | ||
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| PDF Descargar | [ Datasheet PAS5101PE.PDF ] | |
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