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PDF TDF8553J Data sheet ( Hoja de datos )

Número de pieza TDF8553J
Descripción I2C-bus controlled 4 X 50 Watt power amplifier and multiple voltage regulator
Fabricantes NXP Semiconductors 
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TDF8553J
I2C-bus controlled 4 × 50 Watt power amplifier and multiple
voltage regulator
Rev. 01 — 3 December 2008
Objective data sheet
1. General description
1.1 Amplifiers
www.DataSheet4U.com
The TDF8553 has a complementary quad audio power amplifier that uses BCDMOS
technology. It contains four amplifiers configured in Bridge Tied Load (BTL) to drive
speakers for front and rear left and right channels. The I2C-bus allows diagnostic
information of each amplifier and its speaker to be read separately. Both front and both
rear channel amplifiers can be configured independently in line driver mode with a gain of
20 dB (differential output) or amplifier mode with a gain of 26 dB (BTL output).
1.2 Voltage regulators
The TDF8553 has a multiple output voltage regulator with two power switches.
The voltage regulator contains the following:
Four switchable regulators and two standby regulators
Two power switches with loss-of-ground protection and surge protection
Second supply pin to reduce dissipation by means of an external DC-to-DC converter
2. Features
I Amplifiers
N I2C-bus control
N Can drive a 2 load with a battery voltage of up to 16 V and a 4 load with a
battery voltage of up to 18 V
N DC load detection, open, short and present
N AC load (tweeter) detection
N Programmable clip detect; 1 % or 4 %
N Programmable thermal protection pre-warning
N Independent short-circuit protection per channel
N Selectable line driver (20 dB) and amplifier mode (26 dB)
N Loss-of-ground and open VP safe
N All outputs protected from short-circuit to ground, to VP or across the load
N All pins protected from short-circuit to ground
N Soft thermal-clipping to prevent audio holes
N Low battery detection

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TDF8553J pdf
NXP Semiconductors
6. Block diagram
TDF8553J
4 × 50 Watt power amplifier and multiple voltage regulator
www.DataSheet4U.com
BUCAP
36
BACKUP
SWITCH
REGULATOR 6
28 REG6
REGULATOR 2
37 REG2
REFERENCE
VOLTAGE
TEMPERATURE &
LOAD DUMP
PROTECTION VOLTAGE
REGULATOR
VP 35
VDCDC 26
REGULATOR 1
REGULATOR 3
30 REG1
31 REG3
ENABLE
LOGIC
REGULATOR 4
REGULATOR 5
SWITCH 1
SWITCH 2
SDA
SCL
STB
2
4
22
STANDBY/ MUTE
I2C-BUS
INTERFACE
TDF8553J
CLIP DETECT/ DIAGNOSTIC
33 REG4
34 REG5
29 SW1
27 SW2
32 GND
20 VP1
6 VP2
25
DIAG
11
IN1
15
IN2
12
IN3
14
IN4
VP
Fig 1. Block diagram
10
SVR
MUTE
MUTE
MUTE
MUTE
26 dB/
20 dB
26 dB/
20 dB
26 dB/
20 dB
26 dB/
20 dB
PROTECTION/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
PROTECTION/
DIAGNOSTIC
TEMPERATURE & LOAD
DUMP PROTECTION
AMPLIFIER
13 16 8 1 18 24
SGND
PGND1
PGND3
ACGND
PGND2/TAB
PGND4
9 OUT1+
7 OUT1
17 OUT2+
19 OUT2
5 OUT3+
3 OUT3
21 OUT4+
23 OUT4
coa070
TDF8553J_1
Objective data sheet
Rev. 01 — 3 December 2008
© NXP B.V. 2008. All rights reserved.
5 of 47

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TDF8553J arduino
NXP Semiconductors
TDF8553J
4 × 50 Watt power amplifier and multiple voltage regulator
102
ZL
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10
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no load present
(1)
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(2)
www.DataSheet4U.com
load present
1
0 2.5 5 7.5 10
VoM (V)
(1) IoM = < 150 mA.
(2) IoM = > 550 mA.
Fig 3. Tolerance of AC-load detection as a function of output voltage
8.5.7.3 Load detection procedure
1. At start-up, enable the AC or DC-load detection by setting D1 of instruction byte IB1 to
logic 1.
2. After 250 ms the DC load is detected and the mute is released. This is inaudible and
can be implemented each time the IC is powered on.
3. When the amplifier start-up cycle is completed (after 1.5 s), apply an AC signal to the
input, and DC-load bits D5 of each data byte should be read and stored by the
microcontroller.
4. After at least 3 periods of the input signal, the load status can be checked by reading
AC-detect bits D4 of each data byte.
The AC-load peak current counter can be reset by setting bit D1 of instruction
byte IB1 to logic 0 and then to logic 1. Note that this will also reset the DC-load
detection bits D5 in each data byte.
8.5.8 Low headroom protection
The normal DC output voltage of the amplifier is set to half the supply voltage and is
related to the voltage on pin SVR. An external capacitor is connected to pin SVR to
suppress power supply ripple. If the supply voltage drops (at vehicle engine start), the DC
output voltage will follow slowly due to the affect of the SVR capacitor.
The headroom voltage is the voltage required for correct operation of the amplifier and is
defined as the voltage difference between the level of the DC output voltage before the VP
voltage drop and the level of VP after the voltage drop (see Figure 4).
At a certain supply voltage drop, the headroom voltage will be insufficient for correct
operation of the amplifier. To prevent unwanted audible noises at the output, the
headroom protection mode will be activated (see Figure 4). This protection discharges the
capacitors connected to pins SVR and ACGND to increase the headroom voltage.
TDF8553J_1
Objective data sheet
Rev. 01 — 3 December 2008
© NXP B.V. 2008. All rights reserved.
11 of 47

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