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PDF DS32508 Data sheet ( Hoja de datos )
| Número de pieza | DS32508 | |
| Descripción | 6-/8-/12-Port DS3/E3/STS-1 LIU | |
| Fabricantes | Maxim Integrated Products | |
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Hay una vista previa y un enlace de descarga de DS32508 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DS32506/DS32508/DS32512
6-/8-/12-Port DS3/E3/STS-1 LIU
www.maxim-ic.com
GENERAL DESCRIPTION
The DS32506 (6 port), DS32508 (8 port), and
DS32512 (12 port) line interface units (LIUs) are
highly integrated, low-power, feature-rich LIUs for
DS3, E3, and STS-1 applications. Each LIU port in
these devices has independent receive and transmit
paths, a jitter attenuator, full-featured pattern
generator and detector, performance-monitoring
wwwco.DuanttaeSrhse,eat4nUd.caomcomplete set of loopbacks. An on-
chip clock adapter generates all line-rate clocks from
a single input clock. Ports are independently software
configurable for DS3, E3, and STS-1 and can be
individually powered down. Control interface options
include 8-bit parallel, SPI™, and hardware mode.
APPLICATIONS
SONET/SDH and PDH
Multiplexers
ATM and Frame Relay
Equipment
WAN Routers and
Switches
Digital Cross-
Connects
Access Concentrators
CSUs/DSUs
PBXs
DSLAMs
FUNCTIONAL DIAGRAM
LINE IN
DS3, E3,
OR STS-1
LINE OUT
DS3, E3,
OR STS-1
EACH LIU
RXP
RXN
CLK
DATA
Dallas
Semiconductor
DS325xx
TXP
TXN
CLK
DATA
RECEIVE
CLOCK
AND DATA
CONTROL
AND
STATUS
TRANSMIT
CLOCK
AND DATA
FEATURES
Pin-Compatible Family of Products
Each Port Independently Configurable
Receive Clock and Data Recovery for Up to 457
meters (1500 feet) of 75Ω Coaxial Cable
Standards-Compliant Transmit Waveshaping
Uses 1:1 Transformers on Both Tx and Rx
Three Control Interface Options: 8/16-Bit
Parallel, SPI, and Hardware Mode
Jitter Attenuators (One Per Port) Can be Placed
in the Receive Path or the Transmit Path
Jitter Attenuators Have Provisionable Buffer
Depth: 16, 32, 64, or 128 Bits
Built-In Clock Adapter Generates All Line-Rate
Clocks from a Single Input Clock (DS3, E3, STS-1,
12.8MHz, 19.44MHz, 38.88MHz, 77.76MHz)
Per-Port Programmable Internal Line Termination
Requiring Only External Transformers
High-Impedance Tx and Rx, Even When VDD = 0,
Enables Hot-Swappable, 1:1 and 1+1 Board
Redundancy Without Relays
Per-Port BERT for PRBS and Repetitive Pattern
Generation and Detection
Tx and Rx Open and Short Detection Circuitry
Transmit Driver Monitor Circuitry
Receive Loss-of-Signal (LOS) Monitoring
Compliant with ANSI T1.231 and ITU G.775
Automatic Data Squelching on Receive LOS
Large Line Code Performance-Monitoring
Counters for Accumulation Intervals Up to 1s
Local and Remote Loopbacks
Transmit Common Clock Option
Power-Down Capability for Unused Ports
Low-Power 1.8V/3.3V Operation (5V Tolerant I/O)
Industrial Temperature Range: -40°C to +85°C
Small Package: 23mm x 23mm, 484-Pin BGA
IEEE 1149.1 JTAG Support
ORDERING INFORMATION
PART
LIUs TEMP RANGE PIN-PACKAGE
DS32506
DS32506N
DS32508
DS32508N
DS32512
DS32512N
6 0°C to +70°C 484 BGA
6 -40°C to +85°C 484 BGA
8 0°C to +70°C 484 BGA
8 -40°C to +85°C 484 BGA
12 0°C to +70°C 484 BGA
12 -40°C to +85°C 484 BGA
Note: Add the “+” suffix for the lead-free package option.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 103008
1 page  
DS32506/DS32508/DS32512
LIST OF TABLES
Table 1-1. Applicable Telecommunications Standards ............................................................................................... 6
Table 7-1. Short Pin Descriptions .............................................................................................................................. 14
Table 7-2. Analog Line Interface Pin Descriptions .................................................................................................... 17
Table 7-3. Digital Framer Interface Pin Descriptions................................................................................................. 17
Table 7-4. Global Pin Descriptions ............................................................................................................................ 18
Table 7-5. Hardware Interface Pin Descriptions........................................................................................................ 19
Table 7-6. Parallel Interface Pin Descriptions ........................................................................................................... 21
Table 7-7. SPI Serial Interface Pin Descriptions ....................................................................................................... 22
Table 7-8. CLAD Pin Descriptions ............................................................................................................................. 22
Table 7-9. JTAG Pin Descriptions ............................................................................................................................. 23
Table 7-10. Power-Supply Pin Descriptions .............................................................................................................. 23
Table 7-11. Manufacturing Test Pin Descriptions...................................................................................................... 23
Table 8-1. Jitter Generation ....................................................................................................................................... 26
wwwT.aDbaleta8Sh-2ee. tD4US.3coWmaveform Equations ........................................................................................................................ 27
Table 8-3. DS3 Waveform Test Parameters and Limits ............................................................................................ 27
Table 8-4. STS-1 Waveform Equations ..................................................................................................................... 28
Table 8-5. STS-1 Waveform Test Parameters and Limits......................................................................................... 28
Table 8-6. E3 Waveform Test Parameters and Limits............................................................................................... 29
Table 8-7. Transformer Characteristics ..................................................................................................................... 30
Table 8-8. Recommended Transformers................................................................................................................... 30
Table 8-9. Pseudorandom Pattern Generation.......................................................................................................... 37
Table 8-10. Repetitive Pattern Generation ................................................................................................................ 37
Table 8-11. CLAD Clock Source Settings ................................................................................................................. 41
Table 8-12. CLAD Clock Pin Output Settings............................................................................................................ 41
Table 8-13. Global One-Second Reference Source.................................................................................................. 41
Table 8-14. GPIO Pin Global Signal Assignments .................................................................................................... 42
Table 8-15. GPIO Pin Control.................................................................................................................................... 42
Table 8-16. Reset and Power-Down Sources ........................................................................................................... 48
Table 9-1. Overall Register Map................................................................................................................................ 50
Table 9-2. Port Registers........................................................................................................................................... 50
Table 9-3. Global Register Map................................................................................................................................. 51
Table 9-4. Port Common Register Map..................................................................................................................... 62
Table 10-1. JTAG ID Code ........................................................................................................................................ 91
Table 11-1. Recommended DC Operating Conditions .............................................................................................. 92
Table 11-2. DC Characteristics.................................................................................................................................. 93
Table 11-3. Framer Interface Timing ......................................................................................................................... 94
Table 11-4. Receiver Input Characteristics—DS3 and STS-1 Modes....................................................................... 96
Table 11-5. Receiver Input Characteristics—E3 Mode ............................................................................................. 96
Table 11-6. Transmitter Output Characteristics—DS3 and STS-1 Modes................................................................ 97
Table 11-7. Transmitter Output Characteristics—E3 Mode....................................................................................... 97
Table 11-8. Parallel CPU Interface Timing ................................................................................................................ 98
Table 11-9. SPI Interface Timing ............................................................................................................................. 103
Table 11-10. JTAG Interface Timing........................................................................................................................ 105
Table 12-1. Pin Assignments Sorted by Signal Name for DS32506/DS32508/DS32512 ....................................... 106
Table 14-1. Thermal Properties, Natural Convection .............................................................................................. 128
Table 14-2. Theta-JA (θJA) vs. Airflow...................................................................................................................... 128
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5 Page 
DS32506/DS32508/DS32512
5. DETAILED FEATURES
5.1 Global Features
Three interface modes: hardware, 8-/16-bit parallel bus, and SPI serial bus
Independent per-port operation (e.g., line rate, jitter attenuator placement, or loopback type)
Clock, data, and control signals can be inverted to allow a glueless interface to other devices
Manual or automatic one-second update of performance monitoring counters
Each port can be put into a low-power standby mode when not being used
Requires only a single reference clock for all three LIU data rates using internal clock rate adapter
Jitter attenuators can be used in either transmit or receive path
Detection of loss-of-transmit clock
Two programmable I/O pins per port
Optional global write mode configures all LIUs at the same time
www.DaGtalSuheeleest4sUi.ncotemrface to neighboring framer and mapper components
5.2 Receiver
AGC/equalizer block handles from 0 to 22dB of cable loss
Programmable internal termination resistor
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (compliant with ANSI T1.231 and ITU G.775)
Software programmable B3ZS/HDB3 or AMI decoding
Detection and accumulation of bipolar violations (BPV), code violations (CV), and
excessive zeros occurrences (EXZ)
Detection of receipt of B3ZS/HDB3 codewords
Binary or bipolar framer interface
On-board programmable PRBS detector
Per-channel power-down control
5.3 Transmitter
Standards-compliant waveshaping
Programmable waveshaping
Programmable internal termination resistor
Binary or bipolar framer interface
Gapped clock capable up to 78MHz with jitter attenuator in transmit path
Wide 50 ±20% transmit clock duty cycle
Transmit common clock option
Software programmable B3ZS/HDB3 or AMI decoding
Programmable insertion of bipolar violations (BPV), code violations (CV), and excessive zeros (EXZ)
AIS generator: unframed all ones, framed DS3 AIS, and STS-1 AIS-L
Line build-out (LBO) control
High-impedance line-driver output mode to support protection-switching applications
Per-channel power-down control
Output driver monitor
5.4 Jitter Attenuator
One jitter attenuator per port
Fully integrated, requires no external components
Meets all applicable ANSI, ITU, ETSI, and Telcordia jitter transfer and output jitter requirements
Can be placed in the transmit path, receive path or disabled
Programmable FIFO depth: 16, 32, 64, or 128 bits
Overflow and underflow status indications
11 of 130
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS32508.PDF ] | |
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