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PDF DS25LV02 Data sheet ( Hoja de datos )
| Número de pieza | DS25LV02 | |
| Descripción | Low-Voltage 1024-Bit EPROM | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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www.maxim-ic.com
GENERAL DESCRIPTION
The DS25LV02 provides data storage and serial
number identification for battery packs. The low-
voltage Dallas 1-WireÒ interface enables serial
communication on a single battery contact and the
64-bit unique serial number allows multidrop
networking and identification of individual devices.
The 1024-bit EPROM memory is organized as 4
pages of 32 bytes each and supports storage of
battery cell characteristics, charging voltage, current
wwwan.DdattaeSmhpeeetr4aUtu.croemparameters, as well as battery pack
manufacturing data. CRC verification provides data
integrity during communication. The EPROM pages
are in-circuit writable and can be individually locked
to protect data. The DS25LV02 is designed to be
completely backward-compatible with the DS2502 for
existing designs.
APPLICATIONS
Cell Phones/Smartphones
Digital Cameras
MP3 Players
TYPICAL APPLICATION CIRCUIT
DS25LV02
Low-Voltage 1024-Bit EPROM
FEATURES
§ 128 Bytes of EPROM Storage Organized into
Four Separately Lockable Pages
§ Backward-Compatible with DS2502
§ Dallas 1-Wire Interface
§ Input Logic Thresholds Compatible with 1.8V
I/O Supply Rail
§ Unique 64-Bit Serial Number
§ Operates with VDD as Low as 2.2V
§ Tiny, Thin SOT-23 Package
PIN CONFIGURATION
TOP VIEW
5-Pin Thin-SOT (TSOT)
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS25LV02R+U -30°C to +85°C
DS25LV02R+T&
R
-30°C to +85°C
+Denotes lead-free package.
5 Thin SOT
5 Thin SOT in
Tape-and-Reel
1-Wire is a registered trademark of Dallas Semiconductor.
Certain commands, modes, and registers are capitalized for
clarity.
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051106
1 page  
DS25LV02: Low-Voltage 1024-Bit EPROM
EPROM MEMORY DATA FIELD
The DS25LV02 has a linear address space for access to the EPROM data field. The EPROM data field is
organized as 4 pages of 32 bytes each as shown in Table 1. The Read Memory and Read Data/Generate CRC
Memory function commands provide read access to the 1024 bits of the EPROM data field. The Write Memory
function command provides write access to the EPROM data field. When received from the factory, the entire
1024-bit EPROM data field is erased and returns logical 1’s when read. Bits within the data field are one time
programmable. Programming changes the bit value to logical zero from the factory default erased value of a logical
1. Once a bit is programmed, it cannot be set back to a logical 1.
Table 1. EPROM Data Field
ADDRESS (HEX)
DESCRIPTION
0000–001F
PAGE 0 (32 bytes)
READ/WRITE
R/W*
0020–003F
www.DataSheet4U.com
0040–005F
PAGE 1 (32 bytes)
PAGE 2 (32 bytes)
R/W*
R/W*
0060–007F
PAGE 3 (32 bytes)
R/W*
0080–FFFF
Reserved
* One-time write to “0” for each bit.
READ MEMORY [F0h]
The Read Memory command is used to read data from PAGE 0 to PAGE 3 of the 1024-bit EPROM data field. The
bus master follows the command byte with a 2-byte address (TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a
starting byte location within the data field. An 8-bit CRC of the command byte and address bytes is computed by
the DS25LV02 and read back by the bus master to confirm that the correct command word and starting address
were received. If the CRC is deemed to be incorrect by the bus master, the bus master should issue a reset pulse
and repeat the entire sequence. If the CRC is deemed to be correct by the bus master, read time slots can be
issued to receive data from the EPROM data field starting at the initial address. The bus master can issue a reset
pulse at any point or continue to issue read time slots until the end of PAGE 3 of the data field is reached.
If reading continues through the end of PAGE 3, the bus master can issue eight additional read time slots and the
DS25LV02 will respond with a 8-bit CRC of all data bytes read from the initial starting byte through the last byte of
PAGE 3. Terminating the command transaction with a reset pulse prior to reaching the end of PAGE 3 results in a
loss of availability of the 8-bit CRC.
READ DATA/GENERATE 8-BIT CRC [C3h]
The Read Data/Generate 8-bit CRC command is used to read data from PAGE 0 to PAGE 3 of the 1024-bit
EPROM data field. The bus master follows the command byte with a 2-byte address
(TA1 = (T7:T0), TA2 = (T15:T8)) that indicates a starting byte location within the data field. An 8-bit CRC of the
command byte and address bytes is computed by the DS25LV02 and read back by the bus master to confirm that
the correct command word and starting address were received. If the CRC is deemed to be incorrect by the bus
master, the bus master should issue a reset pulse and repeat the entire sequence. If the CRC is deemed to be
correct by the bus master, read time slots can be issued to receive data from the EPROM data field starting at the
initial address. The bus master can issue a reset pulse at any point or continue to issue read time slots until the
end of the 32-byte page is reached. If reading occurs through the end of the 32-byte page, the bus master can
issue eight additional read time slots and the DS25LV02 will respond with an 8-bit CRC of all data bytes read from
the initial starting byte through the last byte of the current page. After the CRC is received, additional read time
slots return data starting with the first byte of the next page. This sequence will continue until the bus master reads
PAGE 3 and its accompanying CRC. Thus each page of data can be considered to be 33 bytes long: the 32 bytes
of user-programmed EPROM data and an 8-bit CRC that gets generated automatically at the end of each page.
The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a reset pulse.
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5 Page 
DS25LV02: Low-Voltage 1024-Bit EPROM
step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master
performs this simple three-step routine on each bit location of the net address. After one complete pass through all
64 bits, the bus master knows the address of one device. The remaining devices can then be identified on
additional iterations of the process. Refer to Chapter 5 of the Book of DS19xx iButton Standards for a
comprehensive discussion of a net address search, including an actual example (www.maxim-ic.com/iButtonBook).
I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the
DS25LV02 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and
read data. The bus master initiates all these types of signaling except the presence pulse.
The initialization sequence required to begin any communication with the DS25LV02 is shown in Figure 5. A
presence pulse following a reset pulse indicates that the DS25LV02 is ready to accept a net address command.
The bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and goes into receive
mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ
pin, the DS25LV02 waits for tPDH and then transmits the presence pulse for tPDL.
wwwF.iDgautarSehe5e.t41U.-cWomire Initialization Sequence
DQ
tRSTL
tPDH
tPDL
tRSTH
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
SLAVE ACTIVE LOW
SLAVE ACTIVE LOW
RESISTOR PULLUP
PACK+
PACK-
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be tSLOT in duration with
a 1ms minimum recovery time, tREC, between cycles. The DS25LV02 samples the 1-Wire bus line between tLOW1_MAX
and tLOW0_MIN after the line falls. If the line is high when sampled, a write 1 occurs. If the line is low when sampled, a
write 0 occurs. The sample window is illustrated in Figure 6. For the bus master to generate a write-1 time slot, the
bus line must be pulled low and then released, allowing the line to be pulled high less than tRDV after the start of the
write time slot. For the host to generate a write-0 time slot, the bus line must be pulled low and held low for the
duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1ms and then release it to allow the DS25LV02 to present
valid data. The bus master can then sample the data tRDV from the start of the read-time slot. By the end of the
read-time slot, the DS25LV02 releases the bus line and allows it to be pulled high by the external pullup resistor. All
read-time slots must be tSLOT in duration with a 1ms minimum recovery time, tREC, between cycles. See Figure 6 and
the timing specifications in the Electrical Characteristics table for more information.
11 of 17
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS25LV02.PDF ] | |
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