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PDF R1EX25512ATA00A Data sheet ( Hoja de datos )
| Número de pieza | R1EX25512ATA00A | |
| Descripción | Serial Peripheral Interface | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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R1EX25512ATA00A
Serial Peripheral Interface
512K EEPROM (64-Kword × 8-bit)
Electrically Erasable and Programmable Read Only Memory
REJ03C0372-0001
Preliminary
Rev.0.01
Dec.19.2008
Description
R1EX25xxx Series is the Serial Peripheral Interface compatible (SPI) EEPROM (Electrically Erasable and
Programmable ROM). It realizes high speed, low power consumption and a high level of reliability by employing
advanced MONOS memory technology and CMOS process and low voltage circuitry technology. It also has a 128-
www.DabytateShpeaegte4Up.rcoogmramming function to make its write operation faster.
Note: Renesas Technology's serial EEPROMs are authorized for using consumer applications such as cellular phones,
camcorders and audio equipments. Therefore, please contact Renesas Technology's sales office before using
industrial applications such as automotive systems, embedded controllers and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Serial Peripheral Interface compatible (SPI bus)
SPI mode 0 (0,0), 3 (1,1)
• Clock frequency: 5 MHz (2.5 V to 5.5 V), 3 MHz (1.8 V to 5.5 V)
• Power dissipation:
Standby: 5 µA (max)
Active (Read): 5 mA (max)
Active (Write): 5 mA (max)
• Automatic page write: 128-byte/page
• Write cycle time: 5 ms
• Endurance: 106 Erase/Write Cycles
• Data retention: 10 Years
• Small size packages: TSSOP-8pin
• Shipping tape and reel
TSSOP-8pin : 3,000 IC/reel
• Temperature range: −40 to +85°C
• Lead free product.
Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Technology’s Sales Dept. regarding specifications.
Rev.0.01, Dec.19.2008, page 1 of 19
1 page  
R1EX25512ATA00A
AC Characteristics
Test Conditions
• Input pulse levels:
VIL = VCC × 0.2
VIH = VCC × 0.8
• Input rise and fall time: ≤ 20 ns
• Input timing reference levels: VCC × 0.5
• Output reference levels: VCC × 0.5
• Output load: 1TTL Gate + 100 pF
(Ta = −40 to +85°C, VCC = 2.5 V to 5.5 V)
Parameter
Symbol
Alt
Min
Max
Unit Notes
Clock frequency
S active setup time
S not active setup time
S deselect time
www.DaStaacShtiveeeth4oUl.dcotimme
S not active hold time
Clock high time
Clock low time
Clock rise time
Clock fall time
Data in setup time
Data in hold time
Clock low hold time after HOLD not active
Clock low hold time after HOLD active
Clock high setup time before HOLD active
Clock high setup time before HOLD not
active
fC
tSLCH
tSHCH
tSHSL
tCHSH
tCHSL
tCH
tCL
tCLCH
tCHCL
tDVCH
tCHDX
tHHCH
tHLCH
tCHHL
tCHHH
fSCK
tCSS1
tCSS2
tCS
tCSH
tCLH
tCLL
tRC
tFC
tDSU
tDH
90
90
90
90
90
90
90
20
30
70
40
60
60
5 MHz
ns
ns
ns
ns
ns
ns
ns
1 µs
1 µs
ns
ns
ns
ns
ns
ns
1
1
2
2
Output disable time
Clock low to output valid
Output hold time
Output rise time
Output fall time
HOLD high to output low-Z
HOLD low to output low-Z
Write time
Erase / Write Endurance
tSHQZ
tDIS
tCLQV
tV
tCLQX
tHO
0
tQLQH
tRO
tQHQL
tFO
tHHQX
tLZ
tHLQZ
tHZ
tW tWC
106
100 ns
60 ns
ns
50 ns
50 ns
50 ns
100 ns
5 ms
cycles
2
2
2
2
2
3
Notes: 1. tCH + tCL ≥ 1/fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Value guaranteed by characterization, not 100% tested in products
106 cycles (Ta = +25°C).
105 cycles (Ta = +85°C).
Rev.0.01, Dec.19.2008, page 5 of 19
5 Page 
R1EX25512ATA00A
Write Disable (WRDI):
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown
in the following figure, to send this instruction to the device, chip select (S) is driven low, and the bits of the instruction
byte are shifted in, on serial data input (D).
The device then enters a wait state. It waits for the device to be deselected, by chip select (S) being driven high. The
Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion
Write Disable (WRDI) Sequence
www.DataSheet4U.com
VIH
S
VIL
VIH
W
VIL
VIH
C
VIL
0 1 2 345 6 7
Instruction
VIH
D
VIL
Q High-Z
Rev.0.01, Dec.19.2008, page 11 of 19
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet R1EX25512ATA00A.PDF ] | |
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