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PDF IDT71V416VL Data sheet ( Hoja de datos )
| Número de pieza | IDT71V416VL | |
| Descripción | (IDT71V416VL/VS) 3.3V CMOS Static RAM 4 Meg | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
IDT71V416VS
IDT71V416VL
Features
◆ 256K x 16 advanced high-speed CMOS Static RAM
◆ JEDEC Center Power / GND pinout for reduced noise.
◆ Equal access and cycle times
– Commercial and Industrial: 10/12/15ns
◆ One Chip Select plus one Output Enable pin
◆ Bidirectional data inputs and outputs directly
LVTTL-compatible
◆ Low power consumption via chip deselect
www.D◆ataUSphpeeerta4nUd.cLoomwer Byte Enable Pins
◆ Single 3.3V power supply
◆ Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
Functional Block Diagram
Description
The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized
as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V416 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71V416 are LVTTL-compatible and operation is from a
single 3.3V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mm package.
Output
OE Enable
Buffer
A0 - A17
Address
Buffers
Chip
CS Select
Buffer
Write
WE Enable
Buffer
BHE
BLE
Byte
Enable
Buffers
©2004 Integrated Device Technology, Inc.
Row / Column
Decoders
4,194,304-bit
Memory
Array
8
Sense
16 Amps
and
Write
Drivers
8
8
8
High
Byte
Output
Buffer
High
Byte
Write
Buffer
8
8
Low
Byte
Output
Buffer
Low
Byte
Write
Buffer
8
8
I/O 15
I/O 8
I/O 7
I/O 0
6478 drw 01
SEPTEMBER 2004
1
DSC-6478/00
1 page  
IDT71V416VS, IDT71V416VL 3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V416S/L10(2)
71V416S/L12
71V416S/L15
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
10 ____ 12 ____ 15 ____ ns
tAA Address Access Time
____ 10 ____ 12 ____ 15 ns
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
____ 10 ____ 12 ____ 15 ns
4 ____ 4 ____ 4 ____ ns
____ 5 ____ 6 ____ 7 ns
tOE Output Enable Low to Output Valid
www.DatOtLaZ(1S)heet4U.cOoumtput Enable Low to Output in Low-Z
tOHZ(1)
Output Enable High to Output in High-Z
____ 5 ____ 6 ____ 7 ns
0 ____ 0 ____ 0 ____ ns
____ 5 ____ 6 ____ 7 ns
tOH Output Hold from Address Change
4 ____ 4 ____ 4 ____ ns
tBE
tBLZ(1)
tBHZ(1)
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
____ 5 ____ 6 ____ 7 ns
0 ____ 0 ____ 0 ____ ns
____ 5 ____ 6 ____ 7 ns
WRITE CYCLE
tWC Write Cycle Time
10 ____ 12 ____ 15 ____ ns
tAW Address Valid to End of Write
8 ____ 8 ____ 10 ____ ns
tCW Chip Select Low to End of Write
8 ____ 8 ____ 10 ____ ns
tBW Byte Enable Low to End of Write
8 ____ 8 ____ 10 ____ ns
tAS Address Set-up Time
0 ____ 0 ____ 0 ____ ns
tWR Address Hold from End of Write
0 ____ 0 ____ 0 ____ ns
tWP Write Pulse Width
8 ____ 8 ____ 10 ____ ns
tDW Data Valid to End of Write
5 ____ 6 ____ 7 ____ ns
tDH
tOW(1)
tWHZ(1)
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
0 ____ 0 ____ 0 ____ ns
3 ____ 3 ____ 3 ____ ns
____ 6 ____ 7 ____ 7 ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.
6478 tbl 10
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC
ADDRESS
tAA
tOH
DATAOUT
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.542
tOH
DATAOUT VALID
6478d06
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT71V416VL.PDF ] | |
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