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PDF ICS843001I-23 Data sheet ( Hoja de datos )
| Número de pieza | ICS843001I-23 | |
| Descripción | FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843001I-23
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843001I-23 is a highly versatile, low
ICS phase noise LVPECL/LVCMOS Synthesizer
HiPerClockS™ which can generate low jitter reference clocks
for a variety of communication applications
and is a member of the HiPerClocksTM family
of high performance clock solutions from ICS.
The dual crystal interface allows the synthesizer to
support up to three communication standards in a given
application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb
Ethernet and Fibre Channel using a 25MHz crystal). The
rms phase jitter performance is typically less than 1ps, thus
www.DmataakSihnegett4hUe.codmevice acceptable for use in demanding
applications such as OC48 SONET, GbE/10Gb Ethernet
and SAN applications. The ICS843001I-23 is packaged in
a small 24-pin TSSOP package.
FEATURES
• One 3.3V LVPECL output pair and
one LVCMOS/LVTTL REF_OUT output
• Selectable crystal oscillator interfaces
or LVCMOS/LVTTL single-ended input
• Crystal and CLK range: 17.5MHz - 29.54MHz
• Able to generate GbE/10GbE/12GbE, Fibre Channel
(1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal
• VCO range: 1.12GHz - 1.3GHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
<1ps (typical) design target
• Supply modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
N2:N0
3
SEL0 Pulldown
SEL1 Pulldown
XTAL_IN0
OSC
XTAL_OUT0
XTAL_IN1
OSC
XTAL_OUT1
CLK Pulldown
00
01
10
11
MR Pulldown
M2:M0 Pullup
3
OE_REF Pulldown
11
Phase
Detector
VCO
10
01
00
M
000 ÷44
001 ÷45
010 ÷48
011 ÷50
100 ÷51
111 ÷64 (default)
N
000 ÷2
001 ÷4
010 ÷5
011 ÷6
100 ÷8 (default)
101 ÷10
110 ÷12
111 ÷16
VCCO_LVCMOS
N0
N1
N2
VCCO_LVPECL
Q
nQ
Q VEE
nQ VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24 REF_OUT
23 VEE
22 OE_REF
21 M2
20 M1
19 M0
18 MR
17 SEL1
16 SEL0
15 CLK
14 XTAL_IN0
13 XTAL_OUT0
ICS843001I-23
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
REF_OUT
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843001AGI-23
www.icst.com/products/hiperclocks.html
REV. B JANUARY 6, 2006
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843001I-23
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
TABLE
4C. POWER
S DC C ,UPPLY
HARACTERISTICS V = V = V VCC CCA CCO_LVPECL, CCO_LVCMOS
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
CC
VCCA
VCCO_LVPECL
VCCO_LVCMOS
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Output Supply Voltage
IEE Power Supply Current
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
2.625
2.625
2.625
2.625
2.5
2.5
2.5
2.5
TBD
TBD
2.625
2.625
2.625
2.625
V
V
V
V
mA
mA
www.DaICtCaASheet4U.coAmnalog Supply Current
ICCO_LVPECL Output Supply Current
ICCO_LVCMOS Output Supply Current
OE_REF = 0
OE_REF = 1, REF_OUT = 29.54MHz
5
TBD
TBD
mA
mA
mA
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V±5% OR 2.5V±5%, OR
VCC = VCCA = 3.3V±5%, VCCO_LVCMOS = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH Input High Voltage
VCC = 3.3V
VCC = 2.5V
VIL Input Low Voltage
VCC = 3.3V
VCC = 2.5V
CLK, SEL0, SEL1,
VCC = VIN = 3.465V
IIH
Input
High Current
OE_REF, MR, N0, N1
N2, M0:M2
or 2.625V
VCC = VIN = 3.465V
or 2.625V
2
1.7
-0.3
-0.3
VCC + 0.3
VCC + 0.3
0.8
0.7
150
5
IIL
Input
Low Current
CLK, SEL0, SEL1,
OE_REF, MR, N0, N1
N2, M0:M2
V = 3.465V or 2.625V,
CC
VIN = 0V
VCC = 3.465V or 2.625V,
-5
-150
VIN = 0V
VOH
Output High
Voltage; NOTE 1
REF_OUT
V = 3.465V
CCO_LVCMOS
VCCO_LVCMOS = 2.625V
2.6
1.8
VOL
Output Low
Voltage; NOTE 1
REF_OUT
VCCO_LVCMOS = 3.465V
or 2.625V
0.5
ΔV/ΔT Input Edge Rate CLK
20% - 80%
TBD
NOTE 1: Output terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram" diagrams.
V
V
V
V
µA
µA
µA
µA
V
V
V
V/ns
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V±5% OR 2.5V±5%, OR
V = V = 3.3V±5%, V
CC CCA
CCO_LVPECL
=
2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
VCCO_LVPECL - 1.4
VCCO_LVPECL - 2.0
0.6
Maximum
VCCO_LVPECL - 0.9
VCCO_LVPECL - 1.7
1.0
Units
V
V
V
843001AGI-23
www.icst.com/products/hiperclocks.html
REV. B JANUARY 6, 2006
5
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843001I-23
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL/LVCMOS
FREQUENCY SYNTHESIZER
CRYSTAL INPUT INTERFACE
The ICS843001I-23 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using an 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
www.DataSheet4U.com
X1
18pF Parallel Cry stal
XTAL_IN
C1
22p
XTAL_OUT
C2
22p
IICCSS88443330201I-23
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT
Zo = 50Ω
FIN
Zo = 50Ω
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843001AGI-23
www.icst.com/products/hiperclocks.html
11
REV. B JANUARY 6, 2006
11 Page | ||
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| PDF Descargar | [ Datasheet ICS843001I-23.PDF ] | |
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