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PDF ICS843001I-22 Data sheet ( Hoja de datos )

Número de pieza ICS843001I-22
Descripción 2.5V LVPECL FREQUENCY SYNTHESIZER
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Integrated
Circuit
Systems, Inc.
ICS843001I-22
FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS843001I-22 is a a highly versatile, low
ICS phase noise LVPECL/LVCMOS Synthesizer
HiPerClockS™ which can generate low jitter reference clocks for
a variety of communications applications and is
a member of the HiPerClocksTM family of high
performance clock solutions from ICS. The dual
crystal interface allows the synthesizer to support up to two
communications standards in a given application (i.e. 1GB
Ethernet with a 25MHz crystal and 1Gb Fibre Channel
using a 25.5625MHz crystal). The rms phase jitter
performance is typically less than 1ps, thus making the
www.DdaetaviScheeeatc4cUe.cpotamble for use in demanding applications such
as OC48 SONET and 10Gb Ethernet. The ICS843001I-22
is packaged in a small 24-pin TSSOP package.
CONTROL INPUT FUNCTION TABLE
Control Input
OE
0
1
FLOAT
Outputs
Q/nQ
REF_OUT
High-Z
High-Z
High-Z
Active
Active
High-Z
BLOCK DIAGRAM
N2:N0
3
SEL0 Pulldown
SEL1 Pulldown
XTAL_IN0
XTAL_OUT0
OSC
XTAL_IN1
XTAL_OUT1
OSC
CLK Pulldown
00
01
10
11
MR Pulldown
M2:M0
3
Phase
Detector
VCO
490MHz -640MHz
M
000 ÷18
001 ÷22
010 ÷24
011 ÷25
100 ÷32 (default)
101 ÷40
FEATURES
• One 3.3V or 2.5V LVPECL output pair and
one LVCMOS/LVTTL output
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• VCO range: 490MHz - 640MHz
• Output frequency range: 490MHz - 640MHz
• Supports the following applications:
SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV
• RMS phase jitter @ 125MHz (1.875MHz - 20MHz):
0.5ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
PIN ASSIGNMENT
VCCO_LVCMOS
N0
N1
N2
VCCO_LVPECL
Q
nQ
VEE
VCCA
VCC
XTAL_OUT1
XTAL_IN1
1
2
3
4
5
6
7
8
9
10
11
12
24 REF_OUT
23 VEE
22 OE
21 M2
20 M1
19 M0
18 MR
17 SEL1
16 SEL0
15 CLK
14 XTAL_IN0
13 XTAL_OUT0
N
000 ÷1
11 001 ÷2
010 ÷3
011 ÷4 (default)
10 100 ÷5
01
00
101 ÷6
110 ÷8
111 ÷10
ICS843001I-22
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
Q
nQ
REF_OUT
OE Pullup/Pulldown
843001AGI-22
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 1, 2005

1 page




ICS843001I-22 pdf
Integrated
Circuit
Systems, Inc.
ICS843001I-22
FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V±10% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH Input High Voltage
VIM Input Medium Voltage
VCC = 3.3V ± 10%
VCC = 2.5V ± 5%
2
1.7
VCC + 0.3
VCC + 0.3
V
V
V
V
VIL Input Low Voltage
www.DaIItHaSheet4UIH.ncipgouhmt Current
CLK, SEL0, SEL1, MR,
M0, M1, N2, OE
M2, N0, N1
IIM
Input
Medium Current
VCC = 3.3V ± 10%
VCC = 2.5V ± 5%
VCC = VIN = 3.63V
or 2.625V
VCC = VIN = 3.63V
or 2.625V
-0.3
-0.3
0.8 V
0.7 V
150 µA
5 µA
µA
IIL
Input
Low Current
CLK, SEL0, SEL1, MR,
M0, M1, N2, OE
M2, N0, N1, OE
VCC = 3.63V or 2.625V,
VIN = 0V
VCC = 3.63V or 2.625V,
-5
-150
VIN = 0V
VOH Output High Voltage; NOTE 1
VCCO_LVCMOS = 3.63V
VCCO_LVCMOS = 2.625V
2.6
1.8
VOL Output Low Voltage: Note 1
VCCO_LVCMOS = 3.63V
or 2.625V
NOTE 1: Outputs terminated with 50Ω to VCCO _LVCMOS/2. See Parameter Measurement Information Section,
"Output Load Test Circuit Diagram".
0.5
µA
µA
V
V
V
TABLE
4D.
LVPECL
DC
CHARACTERISTICS,
V=
CC
V=
CCA
V
CCO_LVPECL
=
3.3V±10%
OR
2.5V±5%, TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL - 2V.
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
Units
V
V
V
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum Units
Fundamental
MHz
14 35.55 MHz
50 Ω
7 pF
1 mW
843001AGI-22
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 1, 2005

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ICS843001I-22 arduino
Integrated
Circuit
Systems, Inc.
ICS843001I-22
FEMTOCLOCKS™CRYSTAL/LVCMOS-TO-
3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1kΩ
resistor can be tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
www.DparotateShcteioent4,Ua.c1okmΩ resistor can be tied from the CLK input to
ground.
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50Ω transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT
Zo = 50Ω
FIN
Zo = 50Ω
50Ω
RTT =
1
((VOH + VOL) / (VCC – 2)) – 2
Zo
50Ω
VCC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Zo = 50Ω
FIN
Zo = 50Ω
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
843001AGI-22
www.icst.com/products/hiperclocks.html
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