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PDF NCP5380 Data sheet ( Hoja de datos )
| Número de pieza | NCP5380 | |
| Descripción | Synchronous Buck Switching Regulator Controller | |
| Fabricantes | ON Semiconductor | |
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NCP5380
7-Bit, Programmable,
Single-Phase, Synchronous
Buck Switching Regulator
Controller
General Description
The NCP5380 is a highly efficient, single−phase, synchronous buck
switching regulator controller. With its integrated drivers, the
NCP5380 is optimized for converting the silver box voltage to the
supply voltage required by high performance Intel chipsets. An
internal 7−bit DAC is used to read a VID code directly from the
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The NCP5380 uses a multimode architecture. It provides
programmable switching frequency that can be optimized for
efficiency depending on the output current requirement. In addition,
the NCP5380 includes a programmable load line slope function to
adjust the output voltage as a function of the load current so that the
core voltage is always optimally positioned for a load transient. The
NCP5380 also provides accurate and reliable current overload
protection and a delayed power−good output. The IC supports
on−the−fly output voltage changes requested by the chipset.
The NCP5380 is specified over the extended commercial
temperature range of 0°C to 85°C and is available in a 32−lead QFN.
Features
• Single−chip Solution
• Fully Compatible with the Intel VR11 CPU Chipset Voltage
Regulator Specifications
• Integrated MOSFET Drivers
• ±8 mV Worst−case Differentially Sensed Core Voltage Error over
Temperature
• Automatic Power−saving Modes Maximize Efficiency During Light
Load Operation
• Soft Transient Control Reduces Inrush Current and Audio Noise
• Independent Current Limit and Load Line Setting Inputs for
Additional Design Flexibility
• Built−in Power−good Masking Supports Voltage Identification (VID)
On−the−fly Transients
• 7−bit, Digitally Programmable DAC
• Short−circuit Protection with Programmable Latch−off Delay
• Current Monitor Output Signal
• 32−lead QFN
• This is a Pb−Free Device
Applications
• Desktop Power Supplies for Next−generation Intel Chipsets
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MARKING
DIAGRAM
1 32
QFN32, 5x5
CASE 488AM
MN SUFFIX
1
NCP5380
AWLYYWWG
G
NCP5380 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION
1
PWRGD
IMON
N/C
FBRTN
FB
COMP
GND
ILIM
NCP5380
(Top View)
VCC
BST
DRVH
SW
PVCC
DRVL
PGND
GND
ORDERING INFORMATION
Device
Package
Shipping†
NCP5380MNR2G QFN−32 5000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
May, 2009 − Rev. 0
1
Publication Order Number:
NCP5380/D
1 page  
NCP5380
ELECTRICAL CHARACTERISTICS VCC = 5 V, FBRTN = 112.5 mV, VVID = 1.25 V, TA = 0°C to 85°C, unless otherwise noted (Note 1).
Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min Typ Max Unit
CURRENT SENSE AMPLIFIER
Gain Bandwidth Product (Note 2)
Slew Rate (Note 2)
Input Common−Mode Range (Note 2)
GBW(CSA)
CCSCOMP = 10 pF
CSFB and CSREF
20 MHz
10 V/ms
0 2V
Output Voltage Range
Output Current
VCSCOMP
ICSCOMP
Source current
Sink current
0.05
−650
1
2
V
mA
mA
SWITCH AMPLIFIER
Common−Mode Range (Note 2)
Input Resistance
www.DataZSehreoeCtu4rUre.cnot Smwitching Threshold
DCM Minimum Off Time Masking
CURRENT LIMIT COMPARATOR
VSW
RSW
VZCS(SW)
tOFFMASK
DCM Mode
SW falling
−400
+200
mV
0.8 1.5 2.0 kW
−6 mV
700 ns
ILIM Voltage
Current Limit Latch Off Delay
VILIM−
VCSCOMP
VILIM−
VCSCOMP
RILIMIT = 5 kW,
VCSREF − VCSCOMP = 100 mV
RILIMIT = 5 kW,
VCSREF − VCSCOMP = 0 mV
From OCP Event to PWRGD De−
assertion
−70 −100 −130 mV
−1 0
1 mV
8 ms
SOFT−START
Soft−Start Time
Soft−Start Delay
tss From FB = 0V to FB = Vboot
1.4 ms
From EN POS Edge to FB = 50 mV
200
ms
SOFT TRANSIENT CONTROL
Output Voltage Positive Slew Rate
Output Voltage Negative Slew Rate
Extended PWRGD Masking
Comparator Threshold
VTH(ST)
|ST − VVID|, ST falling
10 12.5 15 mV⁄ms
−10 −12.5 −15 mV⁄ms
150 mV
SYSTEM LOGIC INPUTS
Input Voltage
Input Current
POWER GOOD
VEN Refers to driving signal level
Logic low, Isink = 1 mA
Logic high, Isource = −5 mA
IEN VEN,VID[1:7] = 0 V
0.2 V < VEN,VID[1:7] ≤ VCC
V
0.3
0.7 V
10 nA
1 mA
CSREF Undervoltage Threshold
CSREF Overvoltage Threshold
CSREF Crowbar (Overvoltage
Protection) Threshold
VUV(CSREF)
VOV(CSREF)
VCB(CSREF)
For VID = 1.2 V
FBRTN = 112.5 mV
−360
150
1.5
−300
200
1.55
−240
250
1.6
mV
mV
V
CSREF Reverse Voltage Detection
Threshold
VRVP(CSREF)
CSREF falling
CSREF rising
−350
−300
−75
PWRGD Output Low Voltage
PWRGD Output Leakage Current
PWRGD Masking Time
VOL(PWRGD)
ISINK(PWRGD) = 4 mA
VPWRDG = 3.3 V
75
100
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
−5
100
0.5
mV
mV
mV
mA
ms
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5
5 Page 
IR = AR X IRAMP
Clock
Oscillator
CR
NCP5380
5V
Flip−Flop
SQ
+
-
RD
Gate
Driver
BST
DRVH
IN SW
DRVL
BST
DRVH
SW
DRVL
VCC
RI L
LOAD
VCC
-
AD + 0.2 V
Ramp
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+
-
+−
+ VDC
S + VCS
FB FBRTN
RA CA
CFB
CB
RFB
CSREF
−
S
+
LLINE
+
-
CSFB
CSCOMP
RCS
CCS
Figure 11. PWM Mode Operation
RPH
Setting Switch Frequency
Master Clock Frequency in PWM Mode
When the NCP5380 runs in PWM, the clock frequency is
set by an external resistor connected from the RT pin to
GND. The frequency varies with the VID voltage: the lower
the VID voltage, the lower the clock frequency. The
variation of clock frequency with VID voltage maintains
constant output ripple and improves power conversion
efficiency at lower VID voltages.
Switching Frequency in RPM Mode
When the NCP5380 operates in RPM mode, its switching
frequency is controlled by the ripple voltage on the COMP
pin. Each time the COMP pin voltage exceeds the RPM pin
voltage threshold level determined by the VID voltage and
the external resistor connected between RPM and ground, an
internal ramp signal is started and DRVH is driven high. The
slew rate of the internal ramp is programmed by the current
entering the RAMP pin. One−third of the RAMP current
charges an internal ramp capacitor (5 pF typical) and creates
a ramp. When the internal ramp signal intercepts the COMP
voltage, the DRVH pin is reset low.
In continuous current mode, the switching frequency of
RPM operation is almost constant. While in discontinuous
current conduction mode, the switching frequency is
reduced as a function of the load current.
Differential Sensing of Output Voltage
The NCP5380 combines differential sensing with a high
accuracy VID DAC, referenced by a precision band gap
source and a low offset error amplifier, In steady−state
mode, the combination of the VID DAC and error amplifier
maintain the output voltage for a worst−case scenario within
±8 mV of the full operating output voltage and temperature
range.
The output voltage is sensed between the FB and FBRTN
pins. FB should be connected through a resistor to the
positive regulation point. FBRTN should be connected
directly to the negative remote sensing point. The internal
VID DAC and precision voltage reference are referenced to
FBRTN thus allowing no load offset to be set using this pin.
Output Current Sensing
The NCP5380 includes a dedicated current sense
amplifier (CSA) to monitor the total output current of the
converter for proper voltage positioning vs. load current and
for overcurrent detection. Sensing the current delivered to
the load is an inherently more accurate method than
detecting peak current or sampling the current across a sense
element, such as the low−side MOSFET. The current sense
amplifier can be configured several ways, depending on
system optimization objectives, and the current information
can be obtained by
• Output inductor ESR sensing without the use of a
thermistor for the lowest cost
• Output inductor ESR sensing with the use of a
thermistor that tracks inductor temperature to improve
accuracy
• Discrete resistor sensing for the highest accuracy
At the positive input of the CSA, the CSREF pin is
connected to the output voltage. At the negative input (that
is, the CSFB pin of the CSA), signals from the sensing
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11
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet NCP5380.PDF ] | |
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