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PDF PCA9506 Data sheet ( Hoja de datos )
| Número de pieza | PCA9506 | |
| Descripción | 40-bit I2C-bus I/O port | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
Rev. 01 — 14 February 2006
Product data sheet
1. General description
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The PCA9506 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 800 mA to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. Output
ports are totem-pole and their logic state changes at the Acknowledge (bank change).
The device can be configured to have each input port to be masked in order to prevent it
from generating interrupts when its state changes and to have the I/O data logic state to
be inverted when read by the system master.
An open-drain interrupt (INT) output pin allows monitoring of the input pins and is
asserted each time a change occurs in one or several input ports (unless masked).
The Output Enable (OE) pin 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).
The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os
as inputs. Three address select pins configure one of 8 slave addresses.
The PCA9506 is available in 56-pin TSSOP and HVQFN packages and is specified over
the −40 °C to +85 °C industrial temperature range.
2. Features
s Standard mode (100 kHz) and Fast mode (400 kHz) compatible I2C-bus serial
interface
s 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
s 40 configurable I/O pins that default to inputs at power-up
s Outputs:
x Totem-pole (10 mA source, 25 mA sink) with controlled edge rate output structure
x Active LOW output enable (OE) input pin 3-states all outputs
x Output state change on Acknowledge
s Inputs:
x Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
x Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
x Polarity Inversion register allows inversion of the polarity of the I/O pins when read
s Active LOW reset (RESET) input pin resets device to power-up default state
s 3 programmable address pins allowing 8 devices on the same bus
1 page  
Philips Semiconductors
6. Pinning information
6.1 Pinning
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
www.DataSheet4U.com
SDA 1
SCL 2
IO0_0 3
IO0_1 4
IO0_2 5
VSS 6
IO0_3 7
IO0_4 8
IO0_5 9
IO0_6 10
VSS 11
IO0_7 12
IO1_0 13
IO1_1 14
IO1_2 15
IO1_3 16
IO1_4 17
VDD 18
IO1_5 19
IO1_6 20
IO1_7 21
IO2_0 22
VSS 23
IO2_1 24
IO2_2 25
IO2_3 26
A0 27
A1 28
PCA9506DGG
Fig 3. Pin configuration for TSSOP56
56 RESET
55 INT
54 IO4_7
53 IO4_6
52 IO4_5
51 VSS
50 IO4_4
49 IO4_3
48 IO4_2
47 IO4_1
46 VDD
45 IO4_0
44 IO3_7
43 IO3_6
42 IO3_5
41 IO3_4
40 IO3_3
39 VSS
38 IO3_2
37 IO3_1
36 IO3_0
35 IO2_7
34 VSS
33 IO2_6
32 IO2_5
31 IO2_4
30 OE
29 A2
002aab491
9397 750 14939
Product data sheet
Rev. 01 — 14 February 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 30
5 Page 
Philips Semiconductors
PCA9506
40-bit I2C-bus I/O port with RESET, OE, and INT
7.3.2 OP0 to OP4 - Output Port registers
These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.
Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).
Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 5: OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Legend: * default value.
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Address Register
Bit
Symbol
Access Value
Description
08h OP0
7 to 0
O0[7:0]
R/W
0000 0000*
Output Port register bank 0
09h OP1
7 to 0
O1[7:0]
R/W
0000 0000*
Output Port register bank 1
0Ah OP2
7 to 0
O2[7:0]
R/W
0000 0000*
Output Port register bank 2
0Bh OP3
7 to 0
O3[7:0]
R/W
0000 0000*
Output Port register bank 3
0Ch OP4
7 to 0
O4[7:0]
R/W
0000 0000*
Output Port register bank 4
7.3.3 PI0 to PI4 - Polarity Inversion registers
These registers allow inversion of the polarity of the corresponding Input Port register.
Px[y] = 0: The corresponding Input Port register data polarity is retained.
Px[y] = 1: The corresponding Input Port register data polarity is inverted.
Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Table 6: PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Legend: * default value.
Address Register
Bit
Symbol
Access Value
Description
10h PI0
7 to 0
P0[7:0]
R/W
0000 0000*
Polarity Inversion register bank 0
11h PI1
7 to 0
P1[7:0]
R/W
0000 0000*
Polarity Inversion register bank 1
12h PI2
7 to 0
P2[7:0]
R/W
0000 0000*
Polarity Inversion register bank 2
13h PI3
7 to 0
P3[7:0]
R/W
0000 0000*
Polarity Inversion register bank 3
14h PI4
7 to 0
P4[7:0]
R/W
0000 0000*
Polarity Inversion register bank 4
9397 750 14939
Product data sheet
Rev. 01 — 14 February 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 30
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