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PDF PCA9502 Data sheet ( Hoja de datos )
| Número de pieza | PCA9502 | |
| Descripción | 8-bit I/O expander | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9502
8-bit I/O expander with I2C-bus/SPI interface
Rev. 03 — 13 October 2006
Product data sheet
1. General description
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The PCA9502 is an 8-bit I/O expander with I2C-bus/SPI host interface. The device comes
in a very small HVQFN24 package, which makes it ideally suitable for hand-held, battery
operated applications.
The device also supports software reset, which allows the host to reset the device at any
time, independent of the hardware reset signal.
2.1 General features
I Selectable I2C-bus or SPI interface
I 3.3 V or 2.5 V operation
I Industrial temperature range: −40 °C to +85 °C
I Eight programmable I/O pins
I Software reset
I Industrial and commercial temperature ranges
I Available in HVQFN24 package
I 16 hardware-selectable slave addresses
2.2 I2C-bus features
I Noise filter on SCL/SDA inputs
I 400 kbit/s (maximum)
I Compliant with I2C-bus Fast-mode
I Slave mode only
2.3 SPI features
I 15 Mbit/s maximum speed
I Slave mode only
I SPI Mode 0
3. Applications
I Factory automation and process control
I Portable and battery operated devices
I Cellular data devices
1 page  
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
7.2 Interrupts
The PCA9502 has interrupt generation capability. The interrupt enable register (IOIntEna)
enables interrupts due to I/O pin change of state, and the IRQ signal in response to an
interrupt generation.
8. Register descriptions
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The programming combinations for register selection are shown in Table 5.
Table 5. Register map - read/write properties
Register name Read mode
IODir
I/O pin direction
IOState
I/O pin states
IOIntEna
I/O interrupt enable register
IOControl
I/O pins control
Write mode
I/O pin direction
n/a
I/O interrupt enable register
I/O pins control
Table 6. PCA9502 internal registers
Register
address
Register
Bit 7
Bit 6
General Register Set
0x0A[1] IODir
bit 7
0x0B[1] IOState bit 7
0x0C[1] IOIntEna bit 7
0x0D[1] reserved reserved
[2] [2]
bit 6
bit 6
bit 6
reserved
[2]
0x0E[1] IOControl reserved reserved
[2] [2]
Bit 5
bit 5
bit 5
bit 5
reserved
[2]
reserved
[2]
Bit 4
bit 4
bit 4
bit 4
reserved
[2]
reserved
[2]
Bit 3
bit 3
bit 3
bit 3
reserved
[2]
SReset
Bit 2
bit 2
bit 2
bit 2
reserved
[2]
reserved
[2]
Bit 1
bit 1
bit 1
bit 1
reserved
[2]
reserved
[2]
Bit 0
bit 0
bit 0
bit 0
reserved
[2]
IOLatch
R/W
R/W
R/W
R/W
R/W
[1] Other addresses 0x00 through 0x09, 0x0F are reserved and should not be accessed (read or write).
[2] These bits are reserved and should be set to 0.
8.1 Programmable I/O pins Direction register (IODir)
This register is used to program the I/O pins direction. Bit 0 to bit 7 control GPIO0 to
GPIO7.
Table 7.
Bit
7:0
IODir register (address 0x0A) bit description
Symbol
Description
IODir
set GPIO pins 7:0 to input or output
0 = input
1 = output
Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending
interrupt will be cleared, that is, the interrupt signal will be negated.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
5 of 25
5 Page 
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
9.3 Addressing
Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The first byte after the START condition carries the address of
the slave device and the read/write bit. Table 11 shows how the PCA9502’s address can
be selected by using A1 and A0 pins. For example, if these 2 pins are connected to VDD,
then the PCA9502’s address is set to 0x90, and the master communicates with it through
this address.
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Table 11.
A1
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
PCA9502 address map
A0 PCA9502 I2C-bus addresses (hex)[1]
VDD
VSS
SCL
0x90 (1001 000X)
0x92 (1001 001X)
0x94 (1001 010X)
SDA
0x96 (1001 011X)
VDD
VSS
SCL
0x98 (1001 100X)
0x9A (1001 101X)
0x9C (1001 110X)
SDA
0x9E (1001 111X)
VDD
VSS
SCL
0xA0 (1010 000X)
0xA2 (1010 001X)
0xA4 (1010 010X)
SDA
0xA6 (1010 011X)
VDD
VSS
SCL
0xA8 (1010 100X)
0xAA (1010 101X)
0xAC (1010 110X)
SDA
0xAE (1010 111X)
[1] X = logic 0 for write cycle; X = logic 1 for read cycle.
9.4 Use of sub-addresses
When a master communicates with the PCA9502 it must send a sub-address in the byte
following the slave address byte. This sub-address is the internal address of the word the
master wants to access for a single byte transfer, or the beginning of a sequence of
locations for a multi-byte transfer. A sub-address is an 8-bit byte. Unlike the device
address, it does not contain a direction (R/W) bit, and like any byte transferred on the bus
it must be followed by an acknowledge.
A register write cycle is shown in Figure 10. The START is followed by a slave address
byte with the direction bit set to ‘write’, a sub-address byte, a number of data bytes, and a
STOP signal. The sub-address indicates which register the master wants to access. and
the data bytes which follow will be written one after the other to the sub-address location.
PCA9502_3
Product data sheet
Rev. 03 — 13 October 2006
© NXP B.V. 2006. All rights reserved.
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