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PDF FCBS0650 Data sheet ( Hoja de datos )
| Número de pieza | FCBS0650 | |
| Descripción | Smart Power Module (SPM) | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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September 8, 2005
FCBS0650
Smart Power Module (SPM)
Features
• UL Certified No.E209204(SPM27-BA package)
• 500V-6A 3-phase MOSFET inverter bridge including control
ICs for gate driving and protection
• Divided negative dc-link terminals for inverter current sensing
applications
• Single-grounded power supply due to built-in HVIC
www.Dat•aSIhsoeleatti4oUn.craotimng of 2500Vrms/min.
• Very low leakage current due to using ceramic substrate
Applications
• AC 200V three-phase inverter drive for small power ac motor
drives
• Home appliances applications like refrigerator.
General Description
It is an advanced smart power module (SPM) that Fairchild has
newly developed and designed to provide very compact and
high performance ac motor drives mainly targeting low-power
inverter-driven application like refrigerator. It combines opti-
mized circuit protection and drive matched to low-loss MOS-
FETs. System reliability is further enhanced by the integrated
under-voltage lock-out and short-circuit protection. The high
speed built-in HVIC provides opto-coupler-less single-supply
MOSFET gate driving capability that further reduce the overall
size of the inverter system design. Each phase current of
inverter can be monitored separately due to the divided nega-
tive dc terminals.
Top View
44mm
Bottom View
26.8mm
Figure 1.
©2005 Fairchild Semiconductor Corporation
FCBS0650 Rev. A
1
www.fairchildsemi.com
1 page  
Absolute Maximum Ratings (TJ = 25°C, Unless Otherwise Specified)
Inverter Part
Symbol
Parameter
Conditions
Rating
Units
VPN
VPN(Surge)
VDSS
± ID
± IDP
PC
TJ
Supply Voltage
Supply Voltage (Surge)
Drain-Source Voltage
Each MOSFET Drain Current
Each MOSFET Drain Current (Peak)
Collector Dissipation
Operating Junction Temperature
Applied between P- NU, NV, NW
Applied between P- NU, NV, NW
TC = 25°C, Peak Sinusoidal Current
TC = 25°C, Under 1ms Pulse Width
TC = 25°C per One Chip
(Note 1)
400
450
500
6
8
26.3
-20 ~ 125
V
V
V
A
A
W
°C
Note:
1. The maximum junction temperature rating of the power chips integrated within the SPM is 150 °C(@TC ≤ 100°C). However, to insure safe operation of the SPM, the average
junction temperature should be limited to TJ(ave) ≤ 125°C (@TC ≤ 100°C)
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Control Part
Symbol
Parameter
Conditions
Rating Units
VCC Control Supply Voltage
Applied between VCC(UH), VCC(VH), VCC(WH), VCC(L) -
COM
20
V
VBS High-side Control Bias Volt- Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) -
age VS(W)
20 V
VIN Input Signal Voltage
Applied between IN(UH), IN(VH), IN(WH), IN(UL), IN(VL),
IN(WL) - COM
-0.3~17
V
VFO Fault Output Supply Voltage Applied between VFO - COM
-0.3~VCC+0.3
V
IFO Fault Output Current
Sink Current at VFO Pin
5 mA
VSC Current Sensing Input Voltage Applied between CSC - COM
-0.3~VCC+0.3
V
Total System
Symbol
Parameter
TSC Short sircuit withstanding time
TC
TSTG
VISO
Module Case Operation Temperature
Storage Temperature
Isolation Voltage
Conditions
VCC = VBS = 13.5 ~ 16.5V, TJ = 125°C,Non-
repetitive,VPN=400V, RShunt=0m
-20°C ≤ TJ ≤ 125°C, See Figure 2
60Hz, Sinusoidal, AC 1 minute, Connection
Pins to ceramic substrate
Rating
10
-20 ~ 100
-40 ~ 125
2500
Units
µs
°C
°C
Vrms
Thermal Resistance
Symbol
Rth(j-c)
Parameter
Conditions
Junction to Case Thermal Inverter MOSFET part (per 1/6 module)
Resistance
Note:
2. For the measurement point of case temperature(TC), please refer to Figure 2.
Min. Typ. Max. Units
- - 3.8 °C/W
Package Marking and Ordering Information
Device Marking
Device
Package
FCBS0650
FCBS0650
SPM27BA
Reel Size
-
Tape Width
-
Quantity
10
FCBS0650 Rev. A
5 www.fairchildsemi.com
5 Page 
CPU
www.DataSheet4U.com
5V-Line
RPF=
4.7kΩ
100 Ω
1nF
CPF=
1nF
SPM
IN(UH) , IN (VH) , IN(W H)
IN (UL) IN (VL) IN(W L)
VF O
COM
Note:
1. RC coupling at each input (parts shown dotted) might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s
printed circuit board. The SPM input signal section integrates 3.3kΩ (typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the sig-
nal voltage drop at input terminal.
2. The logic input is compatible with standard CMOS or LSTTL outputs.
Figure 9. Recommended CPU I/O Interface Circuit
These Values depend on PWM Control Algorithm
15V-Line
RBS
DBS
0.1uF
22uF
RE(H)
One-Leg Diagram of SPM
P
1000uF
1uF
Inverter
Output
N
Note:
1. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.
2. The bootstrap resistor (RBS) should be 3 times greater than RE(H). The recommended value of RE(H) is 5.6Ω, but it can be increased up to 20Ω (maximum) for a slower dv/dt
of high-side.
3. The ceramic capacitor placed between VCC-COM should be over 1uF and mounted as close to the pins of the SPM as possible.
Fig. 10. Recommended Bootstrap Operation Circuit and Parameters
FCBS0650 Rev. A
11 www.fairchildsemi.com
11 Page | ||
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| PDF Descargar | [ Datasheet FCBS0650.PDF ] | |
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