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PDF SC16IS740 Data sheet ( Hoja de datos )

Número de pieza SC16IS740
Descripción Single UART with I2C-bus/SPI interface
Fabricantes NXP Semiconductors 
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No Preview Available ! SC16IS740 Hoja de datos, Descripción, Manual

SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64 bytes of transmit
and receive FIFOs, IrDA SIR built-in support
Rev. 05 — 16 November 2006
Product data sheet
1. General description
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The SC16IS740/750/760 is a slave I2C-bus/SPI interface to a single-channel high
performance UART. It offers data rates up to 5 Mbit/s and guarantees low operating and
sleeping current. The SC16IS750 and SC16IS760 also provide the application with 8
additional programmable I/O pins. The device comes in very small HVQFN24, TSSOP24
(SC16IS750/760) and TSSOP16 (SC16IS740) packages, which makes it ideally suitable
for handheld, battery operated applications. This family of products enables seamless
protocol conversion from I2C-bus or SPI to and RS-232/RS-485 and are fully bidirectional.
The SC16IS760 differs from the SC16IS750 in that it supports SPI clock speeds up to
15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS750, and in that it supports
IrDA SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS760 is functionally and
electrically the same as the SC16IS750. The SC16IS740 is functionally and electrically
identical to the SC16IS750, with the exception of the programmable I/O pins which are
only present on the SC16IS750.
The SC16IS740/750/760’s internal register set is backward-compatible with the widely
used and widely popular 16C450. This allows the software to be easily written or ported
from another platform.
The SC16IS740/750/760 also provides additional advanced features such as auto
hardware and software flow control, automatic RS-485 support, and software reset. This
allows the software to reset the UART at any moment, independent of the hardware reset
signal.
2. Features
2.1 General features
I Single full-duplex UART
I Selectable I2C-bus or SPI interface
I 3.3 V or 2.5 V operation
I Industrial temperature range: 40 °C to +95 °C
I 64 bytes FIFO (transmitter and receiver)
I Fully compatible with industrial standard 16C450 and equivalent
I Baud rates up to 5 Mbit/s in 16× clock mode
I Auto hardware flow control using RTS/CTS
I Auto software flow control with programmable Xon/Xoff characters
I Single or double Xon/Xoff characters
I Automatic RS-485 support (automatic slave address detection)

1 page




SC16IS740 pdf
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
www.DataSheet4U.com
VDD
RESET
SCLK
CS
SO
SI
IRQ
1 k(3.3 V)
1.5 k(2.5 V)
VDD
SC16IS750/760
SPI
I2C/SPI
16C450
COMPATIBLE
REGISTER
SETS
GPIO
REGISTER
XTAL1 XTAL2
VSS
Fig 3. Block diagram of SC16IS750/760 SPI interface
TX
RX
RTS
CTS
4
GPIO[3:0]
GPIO4/DSR
GPIO5/DTR
GPIO6/CD
GPIO7/RI
002aab396
VDD
RESET
SCLK
CS
SO
SI
IRQ
1 k(3.3 V)
1.5 k(2.5 V)
VDD
SC16IS740
SPI
I2C/SPI
16C450
COMPATIBLE
REGISTER
SETS
TX
RX
RTS
CTS
XTAL1 XTAL2
VSS
Fig 4. Block diagram of SC16IS740 SPI interface
002aab972
SC16IS740_750_760_5
Product data sheet
Rev. 05 — 16 November 2006
© NXP B.V. 2006. All rights reserved.
5 of 62

5 Page





SC16IS740 arduino
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.2.2 Auto CTS
Figure 10 shows CTS functional timing. The transmitter circuitry checks CTS before
sending the next data byte. When CTS is active, the transmitter sends the next byte. To
stop the transmitter from sending the following byte, CTS must be deasserted before the
middle of the last stop bit that is currently being sent. The auto CTS function reduces
interrupts to the host system. When flow control is enabled, CTS level changes do not
trigger host interrupts because the device automatically controls its own transmitter.
Without auto CTS, the transmitter sends any data present in the transmit FIFO and a
receiver overrun error may result.
TX
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start bit 0 to bit 7 stop
start bit 0 to bit 7 stop
CTS
002aab041
(1) When CTS is LOW, the transmitter keeps sending serial data out.
(2) When CTS goes HIGH before the middle of the last stop bit of the current character, the transmitter finishes sending the
current character, but it does not send the next character.
(3) When CTS goes from HIGH to LOW, the transmitter begins sending data again.
Fig 10. CTS functional timing
7.3 Software flow control
Software flow control is enabled through the enhanced feature register and the Modem
Control Register. Different combinations of software flow control can be enabled by setting
different combinations of EFR[3:0]. Table 3 shows software flow control options.
Table 3.
EFR[3]
0
1
0
1
X
X
X
1
0
1
0
Software flow control options (EFR[3:0])
EFR[2] EFR[1] EFR[0] TX, RX software flow control
0 X X no transmit flow control
0 X X transmit Xon1, Xoff1
1 X X transmit Xon2, Xoff2
1 X X transmit Xon1 and Xon2, Xoff1 and Xoff2
X 0 0 no receive flow control
X 1 0 receiver compares Xon1, Xoff1
X 0 1 receiver compares Xon2, Xoff2
0 1 1 transmit Xon1, Xoff1
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 transmit Xon2, Xoff2
receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 transmit Xon1 and Xon2, Xoff1 and Xoff2
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 1 1 no transmit flow control
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
SC16IS740_750_760_5
Product data sheet
Rev. 05 — 16 November 2006
© NXP B.V. 2006. All rights reserved.
11 of 62

11 Page







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