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PDF ICS8430-61 Data sheet ( Hoja de datos )
| Número de pieza | ICS8430-61 | |
| Descripción | CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS8430-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
ICS
The ICS8430-61 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Fre-
HiPerClockS™ quency Synthesizer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8430-61 has a select-
able TEST_CLK or crystal inputs. The VCO operates at a fre-
quency range of 250MHz to 500MHz. The VCO frequency is
programmed in steps equal to the value of the input reference
or crystal frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
www.DfaigtuarSahteioent4lUo.gcioc.mFrequency steps as small as 1MHz can be
achieved using a 16MHz crystal or TEST_CLK.
FEATURES
• Dual differential 3.3V LVPECL outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
• Output frequency range: 20.83MHz to 500MHz
• Crystal input frequency range: 14MHz to 27MHz
• VCO range: 250MHz to 500MHz
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 6ps (maximum)
• Cycle-to-cycle jitter: 30ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N2
OSC
0
1
÷ 16
PLL
PHASE DETECTOR
VCO
÷M
÷1
÷1.5
÷2
÷3
÷4
0
÷6
÷8
÷12
1
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
32 31 30 29 28 27 26 25
M5 1
M6 2
M7 3
M8 4
N0 5
N1 6
N2 7
ICS8430-61
24 XTAL_IN
23 TEST_CLK
22 XTAL_SEL
2 1 VCCA
20 S_LOAD
19 S_DATA
18 S_CLOCK
VEE 8
17 MR
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8430AY-61
www.icst.com/products/hiperclocks.html
1
REV. A JULY 22, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS8430-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
Package Thermal Impedance, θJA
Storage Temperature, T
STG
4.6V
-0.5V to VCC + 0.5V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
www.DataSheet4U.com
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
VCC
VCCA
V
CCO
IEE
ICCA
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.135
3.135
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
155
55
Units
V
V
V
mA
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
M0:M8, N0:N2, MR,
Test Conditions
Minimu-
m
Typical
S_LOAD, S_DATA,
VIH
Input
S_CLOCK, nP_LOAD,
High Voltage VCO_SEL, XTAL_SEL
2
TEST_CLK
2
M0:M8, N0:N2, MR,
S_LOAD, S_DATA,
VIL
Input
S_CLOCK, nP_LOAD,
Low Voltage VCO_SEL, XTAL_SEL
-0.3
TEST_CLK
-0.3
M0-M4, M6-M8, N0, N1, MR,
IIH
Input
S_CLOCK, TEST_CLK,
High Current S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
VCC = 3.465V,
IIL
Input
S_DATA, S_LOAD, nP_LOAD
Low Current
M5, XTAL_SEL, VCO_SEL
VIN = 0V
VCC = 3.465V,
VIN = 0V
-5
-150
VOH
Output
High Voltage
TEST; NOTE 1
2.6
Maximum
VCC + 0.3
V + 0.3
CC
0.8
1.3
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
VOL
Output
Low Voltage
TEST; NOTE 1
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
8430AY-61
www.icst.com/products/hiperclocks.html
0.5 V
REV. A JULY 22, 2004
5
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8430-61
500MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-61.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-61 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
www.DataS•heetP4oUw.ceorm(core)MAX = VCC_MAX * IEE_MAX = 3.465V * 155mA = 537.1mW
• Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 537.1mW + 60mW = 597.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.597W * 42.1°C/W = 95°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
67.8°C/W
47.9°C/W
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430AY-61
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11
REV. A JULY 22, 2004
11 Page | ||
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| PDF Descargar | [ Datasheet ICS8430-61.PDF ] | |
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