PDF ICS8430-51 Data sheet ( Hoja de datos )

Número de pieza	ICS8430-51
Descripción	LOW JITTER LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. PRELIMINARY ICS8430-51 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION The ICS8430-51 is a general purpose, dual output ,&6 Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockS™ Synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8430-51 has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 200MHz to 700MHz. With FOUT0 configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved using a 16MHz crystal or reference clock. FOUT1 provides an additional divide by 16 and 180° phase shift. www.DOatuatpShuet efrte4qUu.ceonmcies up to 600MHz can be programmed using the serial or parallel interfaces to the configuration logic. The low jitter and frequency range of the ICS8430-51 make it an ideal clock generator for most clock tree applications. FEATURES • Dual differential 3.3V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Maximum output frequency: 600MHz • Crystal input frequency range: 14MHz to 25MHz • VCO range: 200MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 2.6ps (typical) • Cycle-to-cycle jitter: 17ps (typical) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT VCO_SEL XTAL_SEL TEST_CLK XTAL1 XTAL2 OSC 0 1 ÷ 16 MR S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N2 PLL PHASE DETECTOR VCO ÷M ÷2 0 ÷N 1 CONFIGURATION INTERFACE LOGIC ÷16 M5 M6 M7 M8 N0 N1 N2 VEE FOUT0 nFOUT0 FOUT1 nFOUT1 32 31 30 29 28 27 26 25 1 24 2 23 3 22 4 ICS8430-51 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 XTAL1 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8430AY-51 www.icst.com/products/hiperclocks.html REV. D FEBRUARY 11, 2003 1 1 page Integrated Circuit Systems, Inc. PRELIMINARY ICS8430-51 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE N2 0 0 0 0 1 1 www.DataSheet4U.com 1 1 Inputs N1 0 0 1 1 0 0 1 1 N Divider Value N0 02 14 08 1 16 01 12 04 18 FOUT0, nFOUT0 Output Frequency (MHz) Minimum Maximum 100 350 50 175 25 87.5 12.5 43.75 200 600 100 350 50 175 25 87.5 nFOUT0 FOUT0 nFOUT1 FOUT1 FIGURE 2. FOUTX TIMING DIAGRAM 8430AY-51 www.icst.com/products/hiperclocks.html 5 REV. D FEBRUARY 11, 2003 5 Page Integrated Circuit Systems, Inc. PRELIMINARY ICS8430-51 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors C14 and C15 as close as pos- sible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power www.D(agtraouShnede) pt4laUn.ceoamnd the component power (ground) pins. If VCCA shares the same power supply with VCC, insert the RC filter R7, C11, and C16 in between. Place this RC filter as close to the VCCA as possible. CLOCK TRACES AND TERMINATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system fail- ure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ring- ing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be re- stricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. • The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run ad- jacent to each other.Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock trace on the same layer. Whenever pos- sible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. • Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination schemes can also be used but are not shown in this example. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. 8430AY-51 X1 GND U1 PIN 1 VCC VIA C15 C14 C11 R7 C16 VCCA TL1N Close to the input pins of the receiver R4 R3 TL1 TL1, TL2 are 50 Ohm traces and equal length R2 R1 FIGURE 6B. PCB BOARD LAYOUT FOR ICS8430-51 www.icst.com/products/hiperclocks.html 11 REV. D FEBRUARY 11, 2003 11 Page

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