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Número de pieza | ICS86953I-147 | |
Descripción | 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER | |
Fabricantes | Integrated Circuit Systems | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de ICS86953I-147 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
No Preview Available ! Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
GENERAL DESCRIPTION
ICS
The ICS86953I-147 is a low voltage, low skew
1-to-9 Differential-to-LVCMOS/LVTTL Clock
HiPerClockS™ Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS.The PCLK, nPCLK pair can accept most stan-
dard differential input levels.With output frequencies up to 175MHz,
the ICS86953I-147 is targeted for high performance clock ap-
plications. Along with a fully integrated PLL, the ICS86953I-147
contains frequency configurable outputs and an external feed-
back input for regenerating clocks with “zero delay”.
www.DataSheet4U.com
PIN ASSIGNMENT
FEATURES
• 9 single ended LVCMOS/LVTTL outputs;
(8) clocks, (1) feedback
• PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
• Maximum output frequency: PLL Mode, 175MHz
• VCO range: 250MHz to 700MHz
• Output skew: 75ps (maximum)
• Cycle-to-cycle jitter: 50ps (maximum)
• Static phase offset: 90ps ± 110ps
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible to the MPC953
VDDA
FB_CLK
nc
nc
nc
nc
GND
PCLK
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS86953I-147 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
Q1
VDDO
Q2
GND
Q3
VDDO
Q4
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
BLOCK DIAGRAM
PCLK
nPCLK
FB_CLK
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
86953BYI-147
Phase
Detector
LPF
VCO
0
1
0
÷2 1
0
÷4 1
www.icst.com/products/hiperclocks.html
1
QFB
/7 Q0:Q6
Q7
REV. B APRIL 23, 2004
1 page Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
VDDA,
VDDO
LVCMOS
www.DataGSNhDeet4U.com
SCOPE
Qx
-1.65V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
VDD
nPCLK
PCLK
V
PP
GND
Cross Points
DIFFERENTIAL INPUT LEVEL
Q0:Q7,
QFB
V
DDO
2
tcycle n
V
DDO
2
➤ tcycle n+1
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
V
DDO
2
➤
Qx
Qy
V
DDO
2
V
DDO
2
t sk(o)
OUTPUT SKEW
V
CMR
20%
Clock
Outputs
80%
tR
80%
tF
20%
OUTPUT RISE/FALL TIME
Q0:Q7
QFB
V
DDO
2
Pulse Width
t
PERIOD
odc = t PW
t PERIOD
nPCLK
PCLK
Q0:Q7,
QFB
VDDO
2
t
PD
PROPAGATION DELAY
nPCLK
PCLK
FB_CLK
➤ t(Ø)
VOH
VOL
VOH
VDDO
2
VOL
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PHASE JITTER & STATIC PHASE OFFSET
86953BYI-147
www.icst.com/products/hiperclocks.html
5
REV. B APRIL 23, 2004
5 Page Integrated
Circuit
Systems, Inc.
ICS86953I-147
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
www.DataSheet4U.com
86953BYI-147
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
BBA
NOMINAL
N 32
A -- --
A1 0.05
--
A2 1.35 1.40
b 0.30 0.37
c 0.09 --
D 9.00 BASIC
D1 7.00 BASIC
D2 5.60 Ref.
E 9.00 BASIC
E1 7.00 BASIC
E2 5.60 Ref.
e 0.80 BASIC
L 0.45 0.60
θ 0° --
ccc --
--
Reference Document: JEDEC Publication 95, MS-026
www.icst.com/products/hiperclocks.html
11
MAXIMUM
1.60
0.15
1.45
0.45
0.20
0.75
7°
0.10
REV. B APRIL 23, 2004
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet ICS86953I-147.PDF ] |
Número de pieza | Descripción | Fabricantes |
ICS86953I-147 | 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER | Integrated Circuit Systems |
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