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PDF ICS672-01 Data sheet ( Hoja de datos )

Número de pieza ICS672-01
Descripción QuadraClock Quadrature Delay Buffer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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ICS672-01/02
QuadraClock™ Quadrature Delay Buffer
Description
The ICS672-01 and ICS672-02 are zero delay
buffers that generate four output clocks whose
phases are spaced at 90° intervals. Based on ICS’
proprietary low jitter Phase Locked Loop (PLL)
techniques, each device provides five low skew
outputs, with clock rates up to 84 MHz for the
ICS672-01 and up to 135 MHz for the
ICS672-02. By providing outputs delayed one
quarter clock cycle, the device is useful for systems
wwwr.DeqautaiSrhineget4eUa.rclyomor late clocks.
The ICS672-01/02 include multiplier selections of
x0.5, x1, x2, x3, x4, x5, or x6. They also offer a
mode to power down all internal circuitry and tri
state the outputs. In normal operation, output
clock FBCLK is tied to the FBIN pin.
ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.
Block Diagram
Features
• Packaged in 16 pin narrow SOIC
• Input clock range from 10 MHz to 150 MHz
• Clock outputs from up to 84 MHz (ICS672-01)
and up to 135 MHz (ICS672-02)
• Zero input-output delay
• Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections
• Four accurate (<250 ps) outputs with 0°, 90°,
180°, and 270° phase shift from ICLK, and one
FBCLK (0°)
• Separate supply for output clocks from 2.5V to 5V
• Full CMOS outputs (TTL compatible)
• Tri state mode for board-level testing
• Includes Power Down for power savings
• Advanced, low power, sub-micron CMOS process
• 3.3 V to 5 V operating voltage
• Industrial temperature version available
VDD GND
23
VDDIO
IN
FBIN
PLL
Multiplier
and
Quadrature
Generation
CLK0
CLK90
CLK180
CLK270
CLKFB
S2:S0
3 Control
Logic Power Down + Tri-State
External Feedback
MDS 672-01/02 C
1 Revision 112200
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com

1 page




ICS672-01 pdf
ICS672-01/02
QuadraClock™ Quadrature Delay Buffer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
www.DaINtAaDRShEEeXAet4U.com
12
D
EH
h x 45°
16 pin SOIC narrow
Symbol
A
A1
B
C
D
E
e
H
h
L
Inches
Min Max
0.0532 0.0688
0.0040 0.0098
0.0130 0.0200
0.0075 0.0098
0.3859 0.3937
0.1497 0.1574
.050 BSC
0.2284 0.2440
0.0099 0.0195
0.0160 0.0500
Millimeters
Min Max
1.35 1.75
0.10 0.24
0.33 0.51
0.19 0.24
9.80 10.00
3.80 4.00
1.27 BSC
5.80 6.20
0.25 0.50
0.41 1.27
A1
e
C
B
A
L
Ordering Information
Part/Order Number
ICS672M-01
ICS672M-01T
ICS672M-02
ICS672M-02T
ICS672M-02I
ICS672M-02IT
Marking
ICS672M-01
ICS672M-01
ICS672M-02
ICS672M-02
ICS672M-02I
ICS672M-02I
Shipping packaging
tubes
tape and reel
tubes
tape and reel
tubes
tape and reel
Package
16 pin SOIC
16 pin SOIC
16 pin SOIC
16 pin SOIC
16 pin SOIC
16 pin SOIC
Temperature
0 to 70 °C
0 to 70 °C
0 to 70 °C
0 to 70 °C
-40 to 85 °C
-40 to 85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 672-01/02 C
5 Revision 112200
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com

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