PDF ICS671-15 Data sheet ( Hoja de datos )

Número de pieza	ICS671-15
Descripción	Low Skew Buffer
Fabricantes	Integrated Circuit Systems
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No Preview Available ! ICS671-15 ZERO DELAY, LOW SKEW BUFFER Description The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications. The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a ZDB bank of four outputs running at 33 MHz, and two outputs at 66 MHz from the CPU PLL. This device also provides two 66 MHz zero delay clocks derived from the AGP PLL. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of the feedback clock. www.DTahtaeShICeeSt64U7.1c-o1m5 provides feedback clocks internally for the CPU PLL and the AGP PLL, and with the lowest jitter. Block Diagram Features • Packaged in 24-pin TSSOP • Input-output delay (±300 ps) • Two ZDB 66 MHz outputs from a 66 MHz input AGP clock • Two ZDB 66 MHz outputs, plus four 33 MHz outputs from a 33 MHz input CPU clock • Output-to-output skew is less than 250 ps • Full CMOS outputs with 18 mA output drive capability at TTL levels (at 3.3 V) • Spread SmartTM technology works with spread spectrum clock generators • Advanced, low-power, sub-micron CMOS process • Operating voltage of 3.3 V • Separate hardware output enable pins: OE1, OE2, OE3, OE4, OE5 and OE6 VDD 4 66M_IN 33M_IN AGP PLL CPU PLL /2 OE6 66M_AGPOUT2 66M_AGPOUT1 OE5 66M_CPUOUT2 66M_CPUOUT1 OE4 OE3 33M_PCIOUT4 OE2 33M_PCIOUT3 33M_PCIOUT2 33M_PCIOUT1 OE1 4 GND MDS 671-15 B 1 Revision 021904 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 1 page ICS671-15 ZERO DELAY, LOW SKEW BUFFER Parameter Symbol Conditions Output-to-Output Skew tS Rising edges at VDD/2 66M CPU outputs, Note 1 Output-to-Output Skew tS Rising edges at VDD/2 33M PCI outputs, Note 1 Skew from output of 66M CPU to 33M PCI, equally loaded tS Rising edges at VDD/2 33M PCI outputs Short-term Jitter Input-to-Output Delay www.DataSheet4PUL.cLomLock Time tJA tD tLOCK pealk-to-peak measured at VDD/2 Stable power supply, valid clocks on 66M and 33M Output Enable Time (for OE1 to E6) OE going from low to high with stable output Output Disable Time (for OE1 to E6) OE going high to low tri-state output Note 1: All outputs are equally loaded. Min. -500 Typ. Max. Units 250 500 ps 300 500 ps 300 500 ps 300 +500 1 ps ps ms 1.0 ns 1.0 ns Thermal Characteristics Parameter Symbol Conditions Thermal Resistance Junction to Ambient θJA Still air θJA 1 m/s air flow θJA 2 m/s air flow Thermal Resistance Junction to Case θJC Min. Typ. 77 68 66 25 Max. Units °C/W °C/W °C/W °C/W MDS 671-15 B 5 Revision 021904 Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com 5 Page

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Número de pieza	Descripción	Fabricantes
ICS671-15	Low Skew Buffer	Integrated Circuit Systems

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