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PDF ICS854S204I Data sheet ( Hoja de datos )
| Número de pieza | ICS854S204I | |
| Descripción | LVPECL FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
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LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIAL-
TO-LVDS, LVPECL FANOUT BUFFER
ICS854S204I
GENERAL DESCRIPTION
The ICS854S204I is a low skew, high performance
ICS dual, programmable 1-to-2 Differential-to-LVDS,
HiPerClockS™ LVPECL Fanout Buffer and a member of t h e
HiPerClock S™ family of High Performance Clock
Solutions from IDT. The PCLKx, nPCLKx pairs can
accept most standard differential input levels. With the selection of
SEL_OUT signal, outputs can be selected be to either LVDS or
LVPECL levels. The ICS854S204I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed out-
put and bank skew characteristics make the ICS854S204I
wwidwe.aDlaftoarSthheoeste4Uc.cloocmk distribution applications demanding well
defined performance and repeatability.
FEATURES
• Two programmable differential LVDS or LVPECL output banks
• Two differential clock input pairs
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, SSTL, CML
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVDS levels
with resistor bias on nPCLKx inputs
• Output skew: 15ps (maximum)
• Bank skew: 15ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.15ps (typical)
• Full 3.3V or 2.5V power supply
POWER SUPPLY CONFIGURATION TABLE
• -40°C to 85°C ambient operating temperature
3.3V Operation
2.5V Operation
VDD = 3.3V
VTAP = nc
V = 2.5V
DD
VTAP = 2.5V
• Available in lead-free (RoHS 6) package
SEL_OUT FUNCTION TABLE
SEL_OUT
0
1
Output Level
LVDS
LVPECL
BLOCK DIAGRAM
V
TAP
SEL_OUT Pulldown
PCLKA Pulldown
nPCLKA Pullup
PCLKB Pulldown
nPCLKB Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
PIN ASSIGNMENT
PCLKA
nPCLKA
QA0
nQA0
QA1
nQA1
VTAP
GND
1
2
3
4
5
6
7
8
16 nPCLKB
15 PCLKB
14 QB0
13 nQB0
12 QB1
11 nQB1
10 VDD
9 SEL_OUT
ICS854S204I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
IDT™ / ICS™ LVDS, LVPECL FANOUT BUFFER
1
ICS854S204BGI REV. A JUNE 4, 2008
1 page  
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
TABLE
4I.
LVPECL
DC
CHARACTERISTICS,
V
DD
=
3.3V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions Minimum
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VDD - 2V.
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
VDD - 1.3
VDD - 2.0
0.6
Typical
Maximum
VDD - 0.8
VDD - 1.6
0.9
Units
V
V
V
TABLE 4J. LVPECL DC CHARACTERISTICS, VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum
VOH Output High Voltage; NOTE 1
V Output Low Voltage; NOTE 1
OL
wwVwS.DWIaNGtaShePeet4aUk.-ctoo-mPeak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VDD - 2V.
SEL_OUT = 1
SEL_OUT = 1
SEL_OUT = 1
VDD - 1.3
V - 2.0
DD
0.6
Typical
Maximum
VDD - 0.8
V - 1.55
DD
0.9
Units
V
V
V
TABLE
5A.
LVDS
AC
CHARACTERISTICS,
V
DD
=
3.3V
±
5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
3
500
15
tsk(b) Bank Skew; NOTE 3, 4
15
tjit
Buffer Additive Phase Jitter, RMS;
100MHz, Integration Range:
refer to Additive Phase Jitter Section
12kHz – 20MHz
0.15
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
49
200
51
All parameters measured at 550MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
GHz
ps
ps
ps
ps
ps
%
TABLE 5B. LVDS AC CHARACTERISTICS, VDD = VTAP = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
fMAX
t
PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
tsk(b) Bank Skew; NOTE 3, 4
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
For NOTES, see Table 5A above.
100MHz, Integration Range:
12kHz – 20MHz
20% to 80%
100
49
Typical
0.13
Maximum
3
500
15
15
200
51
Units
GHz
ps
ps
ps
ps
ps
%
IDT™ / ICS™ LVDS, LVPECL FANOUT BUFFER
5
ICS854S204BGI REV. A JUNE 4, 2008
5 Page 
ICS854S204I
LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and
other differential signals. Both V and V must meet the V
SWING
OH
PP
and VCMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
www.DataSheet4U.com
3.3V
R1 R2
50 50
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
3. 3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3. 3V
R3 R4
125 125
3.3V
PCLK
nPCLK HiPerClockS
I nput
R1 R2
84 84
3.3V
Zo = 50 Ohm
3.3V
R1 PCLK
100
nPCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3 R4
84
C1
84
C2
R5
100 - 200
R6
100 - 200
R1 R2
125 125
3.3V
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3 R4
120 120
3.3V
PCLK
R1 R2
120 120
nPCLK
HiPerClockS
PCLK/nPCLK
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
IDT™ / ICS™ LVDS, LVPECL FANOUT BUFFER
11
ICS854S204BGI REV. A JUNE 4, 2008
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ICS854S204I.PDF ] | |
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