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PDF ICS854S013 Data sheet ( Hoja de datos )
| Número de pieza | ICS854S013 | |
| Descripción | 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER | |
| Fabricantes | Integrated Device Technology | |
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PRELIMINARY
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS
FANOUT BUFFER
ICS854S013
General Description
The ICS854S013 is a low skew, high performance
ICS Dual 1-to-3 Differential-to-LVDS Fanout Buffer and
HiPerClockS™ a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The PCLKx,
nPCLKx pairs can accept most standard differential
input levels. The ICS854S013 is characterized to operate from a
3.3V power supply. Guaranteed output and bank skew character-
istics make the ICS854S013 ideal for those clock distribution
applications demanding well defined performance and
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Features
• Two differential LVDS output banks
• Two differential clock input pairs
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
• Output skew: <25ps (typical)
• Bank skew: <50ps (typical)
• Propagation delay: TBD
• Additive phase jitter, RMS: 0.15ps (typical)
• Full 3.3V power supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
PCLKA Pulldown
nPCLKA Pullup
PCLKB Pulldown
nPCLKB Pullup
QA0
nQA0
QA1
nQA1
QA2
nQA2
QB0
nQB0
QB1
nQB1
QB2
nQB2
Pin Assignment
nQA0
QA0
VDD
PCLKA
nPCLKA
PCLKB
nPCLKB
VDD
nQB0
QB0
1
2
3
4
5
6
7
8
9
10
20 QA1
19 nQA1
18 QA2
17 nQA2
16 VDD
15 QB2
14 nQB2
13 QB1
12 nQB1
11 GND
ICS854S013
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS FANOUT BUFFER
1 ICS854S013BG REV. A FEBRUARY 26, 2008
1 page  
ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
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1k
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.15ps (typical)
10k 100k 1M
10M
Offset from Carrier Frequency (Hz)
100M
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
IDT™ / ICS™ LVDS FANOUT BUFFER
5 ICS854S013BG REV. A FEBRUARY 26, 2008
5 Page 
ICS854S013
LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S013.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854S013 is the sum of the core power plus the power dissipated in the load(s). The following is the
power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 135mA = 467.77mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
wwThwe.DmaataxSimheuemt4rUe.ccoommmended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 87.2°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.468W * 87.2°C/W = 110.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
87.2°C/W
1
82.9°C/W
2.5
80.7°C/W
IDT™ / ICS™ LVDS FANOUT BUFFER
11 ICS854S013BG REV. A FEBRUARY 26, 2008
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS854S013.PDF ] | |
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