PDF ICS8547 Data sheet ( Hoja de datos )

Número de pieza	ICS8547
Descripción	1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. ICS8547 HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS GENERAL DESCRIPTION The ICS8547 is a Hex low skew, high perfor- ,&6 mance 1-to-2 Differential-to-LVDS Clock Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8547 provides a low power, low noise, point-to-point solu- tion for distributing clock signals over controlled impedances of 100Ω. The ICS8547 has six selectable clock inputs. The CLKx, nCLKx pairs can accept any differential input levels and translates them to 3.3V LVDS output levels. www.DGautaaSrhaenetet4eUd.cooumtput and part-to-part skew specifications make the ICS8547 ideal for those applications demanding well defined performance and repeatability. FEATURES • 12 LVDS outputs • Selectable CLKx, nCLKx inputs • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Translates any differential input signal (LVPECL, LVHSTL, SSTL, DCM) to LVDS levels without external bias networks • Translates any single-ended input signal to LVDS with resistor bias on nCLKx input • Output skew: 250ps (maximum) • Bank skew: 15ps (maximum) • Part-to-part skew: 500ps (maximum) • Propagation delay: 1.8ns (maximum) • 3.3V operating supply • 0°C to 85°C ambient operating temperature • Industrial temperature information available upon request BLOCK DIAGRAM CLK0 nCLK0 CLK1 nCLK1 CLK2 nCLK2 CLK3 nCLK3 CLK4 nCLK4 CLK5 nCLK5 PIN ASSIGNMENT Q0A nQ0A Q0B nQ0B Q1A nQ1A Q1B nQ1B Q2A nQ2A Q2B nQ2B Q3A nQ3A Q3B nQ3B Q4A nQ4A Q4B nQ4B Q5A nQ5A Q5B nQ5B Q4A nQ4A nQ4B Q4B nCLK4 CLK4 CLK5 nCLK5 Q5B nQ5B nQ5A Q5A 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 7 ICS8547 31 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24 Q2A nQ2A nQ2B Q2B nCLK2 CLK2 CLK1 nCLK1 Q1B nQ1B nQ1A Q1A 48-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ICS8547AY www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 4, 2003 1 page Integrated Circuit Systems, Inc. ICS8547 HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum f MAX tPD tsk(o) Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 5 ƒ≤ 500MHz 700 1.2 1.5 1.8 250 tsk(b) Bank Skew; NOTE 3, 5 15 tsk(pp) Part-to-Part Skew; NOTE 4, 5 500 tR / tF Output Rise/Fall Time www.DaotdacSheet4UO.cuotmput Duty Cycle 20% to 80% ƒ≤ 300MHz 300MHz < ƒ≤ 500MHz 250 45 50 40 All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured from at the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 4: Defined as between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 550 55 60 Units MHz ns ps ps ps ps % % ICS8547AY www.icst.com/products/hiperclocks.html 5 REV. A FEBRUARY 4, 2003 5 Page Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX www.DataSheet4U.com ICS8547 HEX, LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS CLOCK BUFFERS ICS8547AY TABLE 6. PACKAGE DIMENSIONS SYMBOL JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBC MINIMUM NOMINAL N 48 A -- -- A1 0.05 -- A2 1.35 1.40 b 0.17 0.22 c 0.09 -- D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 q 0° -- ccc -- -- Reference Document: JEDEC Publication 95, MS-026 MAXIMUM 1.60 0.15 1.45 0.27 0.20 0.75 7° 0.08 www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 4, 2003 11 Page

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