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PDF ICS8545I-02 Data sheet ( Hoja de datos )
| Número de pieza | ICS8545I-02 | |
| Descripción | 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer | |
| Fabricantes | Integrated Device Technology | |
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Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS
Fanout Buffer
ICS8545I-02
DATASHEET
General Description
The ICS8545I-02 is a low skew, high performance
ICS 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer
HiPerClockS™ and a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. Utilizing Low
Voltage Differential Signaling (LVDS) the ICS8545I-02
provides a low power, low noise, solution for distributing clock signals
over controlled impedances of 100Ω. The ICS8545I-02 accepts an
LVCMOS/LVTTL input level and translates it to 3.3V LVDS output
levels.
Guaranteed output and part-to-part skew characteristics make the
IwCwSw85.D4a5It-a0S2heideeta4Ul f.ocrotmhose applications demanding well defined
performance and repeatability.
Features
• Four differential LVDS output pairs
• Two LVCMOS/LVTTL clock inputs to support redundant
or selectable frequency fanout applications
• Maximum output frequency: 350MHz
• Translates LVCMOS/LVTTL input signals to LVDS levels
• Output skew: 60ps (maximum)
• Part-to-part skew: 450ps (maximum)
• Propagation delay: 1.45ns (maximum)
• Additive phase jitter, RMS: 0.14ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
CLK_EN Pullup
CLK1 Pulldown
CLK2 Pulldown
CLK_SEL Pulldown
00
11
nD
Q
LE
OE Pullup
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
GND
CLK_EN
CLK_SEL
CLK1
nc
CLK2
nc
OE
GND
VDD
1
2
3
4
5
6
7
8
9
10
20 Q0
19 nQ0
18 VDD
17 Q1
16 nQ1
15 Q2
14 nQ2
13 GND
12 Q3
11 nQ3
ICS8545I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS8545AGI-02 REVISION A JULY 29, 2009
1
©2009 Integrated Device Technology, Inc.
1 page  
ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tPD
tjit
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz, Integration Range:
12kHz – 20MHz
1.0
0.14
350 MHz
1.45 ns
ps
tsk(o)
Output Skew; NOTE 2, 4
60 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
450 ps
tR / tF
Output Rise/Fall Time
20% to 80%
150
700 ps
odc Output Duty Cycle; NOTE 5
ƒ ≤ 166MHz
ƒ> 166MHz
45
40
55 %
60 %
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NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Measured using 50% duty cycle.
ICS8545AGI-02 REVISION A JULY 29, 2009
5
©2009 Integrated Device Technology, Inc.
5 Page 
ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
91.1°C/W
1
86.7°C/W
2.5
84.6°C/W
Transistor Count
The transistor count for ICS8545I-02 is: 360
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Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
α 0°
8°
aaa 0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8545AGI-02 REVISION A JULY 29, 2009
11
©2009 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS8545I-02.PDF ] | |
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