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PDF ICS85454-01 Data sheet ( Hoja de datos )

Número de pieza ICS85454-01
Descripción DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
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Integrated
Circuit
Systems, Inc.
ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
GENERAL DESCRIPTION
The ICS85454-01 is a 2:1/1:2 Multiplexer and
ICS a member of the HiPerClockSTM family of high
HiPerClockS™ performance clock solutions from ICS. The 2:1
Multiplexer allows one of 2 inputs to be select-
ed onto one output pin and the 1:2 MUX
switches one input to both of two outputs. This device
may be useful for multiplexing multi-rate Ethernet PHYs
which have 100Mbit and 1000Mbit transmit/receive
pairs onto an optical SFP module which has a single
transmit/receive pair. Another mode allows loop back
www.DtaetsatiSnhgeeatn4dU.caollomws the output of a PHY transmit pair to be
routed to the PHY input pair. For examples, please refer to
the Application Information section of the data sheet.
The ICS85454-01 is optimized for applications requiring
very high performance and has a maximum operating
frequency in 2.5GHz. The device is packaged in a small,
3mm x 3mm VFQFN package, making it ideal for use on
space-constrained boards.
FEATURES
Dual 2:1/1:2 MUX
Three LVDS outputs
Three differential inputs
Differential inputs can accept the following differential
levels: LVPECL, LVDS, CML
Loopback test mode available
Maximum output frequency: 2.5GHz
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.05ps (typical)
Propagation delay: 550ps (maximum)
2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
SELB
INB
nINB
QB
nQB
0
01
1
PIN ASSIGNMENT
INA0
nINA0
LOOP0
QA0
nQA0
16 15 14 13
QA0 1
12 INA0
nQA0 2
11 nINA0
QA1 3
10 INA1
nQA1 4
9 nINA1
5678
INA1
nINA1
LOOP1
QA1
nQA1
ICS85454-01
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
85454AK-01
SELA
www.icst.com/products/hiperclocks.html
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REV. B JUNE 16, 2006

1 page




ICS85454-01 pdf
Integrated
Circuit
Systems, Inc.
ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
www.DataSheet4U.com
0
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
-10
Additive Phase Jitter at
-20 622.08MHz (12kHz - 20MHz)
-30 = 0.05ps (typical)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k 10k 100k 1M
OFFSET FROM CARRIER FREQUENCY (HZ)
10M 100M
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
85454AK-01
www.icst.com/products/hiperclocks.html
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REV. B JUNE 16, 2006

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ICS85454-01 arduino
Integrated
Circuit
Systems, Inc.
ICS85454-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVDS MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85454-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85454-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
www.DataS·heetP4oUw.ceorm_MAX = VDD_MAX * IDD_MAX = 2.625V * 90mA = 236.3mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
no air flow of and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.236W * 51.5°C/W = 97.2°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-PIN VFQFN, FORCED CONVECTION
θJA vs. 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
51.5°C/W
85454AK-01
www.icst.com/products/hiperclocks.html
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