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PDF ICS85411I Data sheet ( Hoja de datos )

Número de pieza ICS85411I
Descripción 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Fabricantes Integrated Device Technology 
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No Preview Available ! ICS85411I Hoja de datos, Descripción, Manual

LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-
LVDS FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85411I is a low skew, high performance
ICS 1-to-2 Differential-to-LVDS Fanout Buffer and a
HiPerClockS™ member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The CLK,
nCLK pair can accept most standard differential in-
put levels.The ICS85411I is characterized to operate from
a 3.3V power supply. Guaranteed output and par t-to-par t
skew characteristics make the ICS85411I ideal for those
clock distribution applications demanding well defined per-
for mance and repeatability.
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ICS85411I
FEATURES
Two differential LVDS outputs
One differential CLK, nCLK clock input
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 650MHz
Translates any single ended input signal to
LVDS levels with resistor bias on nCLK input
Output skew: 25ps (maximum)
Part-to-part skew: 300ps (maximum)
Additive phase jitter, RMS: 0.05ps (typical)
Propagation delay: 2.5ns (maximum)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead free (RoHS 6)
packages
BLOCK DIAGRAM
CLK
nCLK
Q0
nQ0
Q1
nQ1
PIN ASSIGNMENT
Q0 1
nQ0 2
Q1 3
nQ1 4
8 VDD
7 CLK
6 nCLK
5 GND
ICS85411I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
IDT/ ICSDIFFERENTIAL-TO-LVDS FANOUT BUFFER
1
ICS85411AMI REV. B NOVEMBER 7, 2007

1 page




ICS85411I pdf
ICS85411I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
0
-10
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-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k 100k
Input/Output Additive Phase
Jitter @ 200MHz (12kHz to 20MHz)
= 0.05ps typical
1M
10M
100M
500M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependant on the input source and measurement equipment.
IDT/ ICSDIFFERENTIAL-TO-LVDS FANOUT BUFFER
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ICS85411AMI REV. B NOVEMBER 7, 2007

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ICS85411I arduino
ICS85411I
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85411I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85411I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 10% = 3.63V, which gives worst case results.
DD
Power (core) = V * I = 3.63V * 50mA = 181.5mW
MAX
DD_MAX
DD_MAX
ww2w. .DJautnacStihoeneTt4eUm.cpoemrature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows:
Tj
=
θJA
*
Pd_total
+
T
A
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming a
JA
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.182W * 103.3°C/W = 103.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θ FOR 8-LEAD SOIC, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
153.3°C/W
112.7°C/W
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT/ ICSDIFFERENTIAL-TO-LVDS FANOUT BUFFER
11
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