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PDF ICS854057 Data sheet ( Hoja de datos )

Número de pieza ICS854057
Descripción 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
Fabricantes Integrated Circuit Systems 
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No Preview Available ! ICS854057 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
GENERAL DESCRIPTION
ICS
The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul-
tiplexer which can operate up to 2GHz and is a
HiPerClockS™ member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The PCLK,
nPCLK pairs can accept most standard differen-
tial input levels. Internal termination is provided on each dif-
ferential input pair. The ICS854057 operates using a 2.5V sup-
ply voltage. The fully differential architecture and low propa-
gation delay make it ideal for use in high speed multiplexing
applications. The select pins have internal pulldown resistors.
www.DLaetaavSihnegeot4nUe.cinopmut unconnected (pulled to logic low by the in-
ternal resistor) will transform the device into a 2:1 multiplexer.
The SEL1 pin is the most significant bit and the binary num-
ber applied to the select pins will select the same numbered
data input (i.e., 00 selects PCLK0, nPCLK0).
FEATURES
High speed differential multiplexer.The device can be
configured as either a 4:1 or 2:1 multiplexer
Single LVDS output
4 selectable PCLK, nPCLK inputs with internal termination
PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Output frequency: >2GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: 800ps (maximum)
Additive phase jitter, RMS: 66fs (typical)
2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both, Standard and RoHS/Lead-Free compliant
packages
BLOCK DIAGRAM
VT0
50
PCLK0
nPCLK0
VT1
50
50
PCLK1
nPCLK1
50
VT2
50
PCLK2
nPCLK2
VT3
50
50
PCLK3
nPCLK3
50
SEL1 Pulldown
SEL0 Pulldown
854057AG
PIN ASSIGNMENT
00
01 Q
10 nQ
11
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 PCLK3
18 VT3
17 nPCLK3
16 Q
15 nQ
14 PCLK2
13 VT2
12 nPCLK2
11 GND
ICS854057
20-Lead TSSOP
4.40mm x 6.50mm x 0.925mm body package
G Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A JULY 18, 2005

1 page




ICS854057 pdf
Integrated
Circuit
Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
www.DataSheet4U.com
0
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
-10 Additive Phase Jitter @ 622.08MHz
-20 (12kHz to 20MHz)
-30 = 66fs typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k 100k 1M 10M 100M 500M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
854057AG
www.icst.com/products/hiperclocks.html
5
REV. A JULY 18, 2005

5 Page





ICS854057 arduino
Integrated
Circuit
Systems, Inc.
ICS854057
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER
WITH INTERNAL INPUT TERMINATION
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
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Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854057 is: 346
854057AG
www.icst.com/products/hiperclocks.html
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REV. A JULY 18, 2005

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