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PDF AI2152 Data sheet ( Hoja de datos )
| Número de pieza | AI2152 | |
| Descripción | Digital Signal Processor | |
| Fabricantes | A1 PROs | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AI2152 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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1 A1 PROs
A1 PROs
Ver0.12
Ai2152
Digital Signal Processor for Color CCD Cameras
GENERAL DESCRIPTION
The Ai2152 is a digital signal-processing chip for color video camera. It includes timing generator
and digital/analog output. Supports 250K/380K NTSC system CCD sensors and 290K/440K PAL
system CCD sensors with complementary color filter. It also provided line lock function.
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FEATURES
‧ Support Ye, Cyan, Magenta, Green complementary color filter CCD sensors for
NTSC : Ai325CA(250K), Ai338CA(380K)
PAL : Ai329CA(290K), Ai344CA(440K)
‧ Support external EEPROM to store parameter.
‧ Built-in auto white balance control.
‧ Built-in auto exposure control.
‧ Built-in 9bit digital to analog converter.
‧ Built-in mirror function.
‧ Built-in blemish compensation circuit storing the data in EEPROM, up to 200 blemish pixels.
‧ Support analog video output and UYVY (proprietary format) digital output.
‧ Built-in timing generator for vertical driver and CDS/AGC/ADC peripheral chips.
‧ Support line lock function.
‧ Single 3.3V power supply. (Horizontal drive pins can be 3.3V/5V)
‧ LQFP-80. (0.4mm pin pitch)
‧ Support user Definable GPIO.
‧ Programmable CCD Timing Driving Current.
‧ Programmable pull-up GPIO pin
1
1 page  
Pin Symbol
61 VD
62 XV1
63 XV2
64 XV3
65 XV4
66 VCC
67 GND
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68 XSG1
69 XSG2
70 XSUB
71 HVCC
72 HGND
73 RG
74 H1
75 H2
76 VCC
77 GND
78 AFE_CSN
79 SHD
80 SHP
I : Input
O : Output
P : Power
B : Bi-direction
Ai2152
I/O, P/G
O
O
O
O
O
P
P
O
O
O
P
P
O
O
O
P
P
O
O
O
Description
VSYNC for Digital output
Vertical Shift Register Clock1
Vertical Shift Register Clock2
Vertical Shift Register Clock3
Vertical Shift Register Clock4
Power (+3.3V)
GND
CCD Sensor Charge Readout Pulse Output TG1
CCD Sensor Charge Readout Pulse Output TG2
CCD Discharge Pulse Output
Power (+3.3V or +5V for H1, H2, RG)
GND
Reset Gate Pulse Output
H1 Clock Output for CCD Horizontal Register Drive
H2 Clock Output for CCD Horizontal Register Drive
Power (+3.3V)
GND
AFE 3-Wire CSN
Data Sample and Hold Pulse
Pre Charge Level Sample and Hold Pulse
5
5 Page 
Ai2152
ADDRESS
NAME
BIT
CONTENTS
2F
(1087h)
Reserved
7:2
30
(1088h)
OBCLP_H_STOP[7:0]
7:0
Horizontal stop for OBCLP. (Unit: 1 pixel)
(Note: active region is not include stop pixel)
31
(1089h)
OBCLP_H_STOP[9:8]
Reserved
1:0
7:2
32 H_START[5:0]
(108Ah)
Reserved
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33 V_START[3:0]
(108Bh)
Reserved
5:0 Horizontal start pixel of each line. (Unit: 1 pixel)
7:6
3:0 Vertical start line of each field. (Unit: 1 Line)
7:4
34
(108Ch)
H_SIZE[7:0]
7:0 Horizontal size of each line. (Unit: 4 pixel)
35
(108Dh)
V_SIZE[7:0]
7:0 Vertical size of each field. (Unit: 2 Line)
36
(00DEh)
C_M11_MT[7:0]
7:0 C_M11 of Color matrix at middle color temperature.
37
(00DFh)
C_M12_MT[7:0]
7:0 C_M12 of Color matrix at middle color temperature.
38
(00E0h)
C_M13_MT[7:0]
7:0 C_M13 of Color matrix at middle color temperature.
39
(00E1h)
C_M21_MT[7:0]
7:0 C_M21 of Color matrix at middle color temperature.
3A
(00E2h)
C_M22_MT[7:0]
7:0 C_M22 of Color matrix at middle color temperature.
3B
(00E3h)
C_M23_MT[7:0]
7:0 C_M23 of Color matrix at middle color temperature.
3C
(00E4h)
C_M31_MT[7:0]
7:0 C_M31 of Color matrix at middle color temperature.
3D
(00E5h)
C_M32_MT[7:0]
7:0 C_M32 of Color matrix at middle color temperature.
3E
(00E6h)
C_M33_MT[7:0]
7:0 C_M33 of Color matrix at middle color temperature.
3F
(1098h)
ODD_OFFSET[7:0]
OFFSET compensation for ODD field.
7:0 (Unit: 1 level at 8 bits)
Note: It is sync with VSYNC.
40
(1099h)
EVEN_OFFSET[7:0]
OFFSET compensation for EVEN field.
7:0 (Unit: 1 level at 8 bits)
Note: It is sync with VSYNC.
41
(109Ah)
GLB_GAIN[4:0]
Reserved
4:0
Global GAIN control Æ Gain = (1+GLB_GAIN/32)
Note: It is sync with VSYNC.
7:5
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AI2152.PDF ] | |
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