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PDF PA7572 Data sheet ( Hoja de datos )
| Número de pieza | PA7572 | |
| Descripción | Programmable Electrically Erasable Logic Array | |
| Fabricantes | Anachip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PA7572 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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PA7572 PEEL Array™
Programmable Electrically Erasable Logic Array
Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and -40
to +85 °C temperatures
wwIdwe.aDlaftoaSrhCeoetm4Ub.cinoamtorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
CMOS Electrically Erasable Technology
- Reprogrammable in 40-pin DIP, 44-pin PLCC and
TQFP packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
General Description
The PA7572 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on Anachip’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7572 offers a
versatile logic array architecture with 24 I/O pins, 14 input
pins and 60 registers/latches (24 buried logic cells, 12 input
registers/latches, 24 buried I/O registers/latches). Its logic
array implements 100 sum-of-products logic functions
divided into two groups each serving 12 logic cells. Each
group shares half (60) of the 120 product-terms available.
The PA7572’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7572 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. The
PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
and 66.6MHz (fMAX) at moderate power consumption
140mA (100mA typical). Packaging includes 40-pin DIP
and 44-pin PLCC (see Figure 1). Anachip and popular
third-party development tool manufacturers provide
development and programming support for the PA7572.
Figure 1. Pin Configuration
Figure 2. Block Diagram
DIP (600 mil)
I/C L K 1
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/C L K 2
TQFP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PLCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 4039 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 13 14 151617 18 19 20 21 22
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
08-15-001A
I/C L K
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
GND
2 Input/
G lobal Clock Pins
12 Input Pins
Input
Cells
( IN C )
Global Cells
Input Cells
I/O Cells
Logic Control Cells
PA7572
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK 2
Global
Cells
124 (62X2)
Array Inputs
true and
2 complement
12 24
I/O
Cells
(IO C)
24 I/O Pins
Lo gic
A rra y
24 Buried
logic
Logic
A
B
Control
C Cells
D (LCC)
24
Logic
func tions
to I/O cells
4 sum terms
5 product terms
for Global Cells
96 sum terms
(four per LCC)
24
24 Logic Control Cells
up to 3 output functions per cell
(72 total output functions
possible)
08-15-002A
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
1 page  
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful PLACE Development Software
(free to qualified PLD designers).
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
wwalwlo.DwaintagShtheeete4Uff.eccotmiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
internal signals to be simulated and analyzed via a
waveform display.(See Figure 12, Figure 13, Figure 14)
unexpected changes to be made quickly and without waste.
Programming of PEEL™ Arrays is supported by many
popular third party programmers.
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
Figure 13. PLACE LCC and IOC Screen
Figure 12. PLACE Architectural Editor
PEEL™ Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT’s
PEEL™ Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEEL™ Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EE-
reprogrammability is also useful for production, allowing
Anachip Corp.
www.anachip.com.tw
5/10
Figure 14. PLACE Simulator Screen
Rev. 1.0 Dec 16, 2004
5 Page | ||
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