PDF K4S641632K Data sheet ( Hoja de datos )

Número de pieza	K4S641632K
Descripción	64Mb K-die SDRAM
Fabricantes	Samsung semiconductor
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No Preview Available ! K4S640832K K4S641632K Synchronous DRAM 64Mb K-die SDRAM Specification www.DataSheet4U.com INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. 1 of 14 Rev. 1.1 February 2006 1 page K4S640832K K4S641632K FUNCTIONAL BLOCK DIAGRAM Synchronous DRAM Data Input Register Bank Select CLK ADD www.DataSheet4U.com 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 2M x 8 / 1M x 16 Column Decoder LCKE LRAS LCBR LWE LCAS Latency & Burst Length Programming Register LWCBR Timing Register LWE LDQM DQi LDQM CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. 5 of 14 Rev. 1.1 February 2006 5 Page K4S640832K K4S641632K Synchronous DRAM AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time CAS latency=3 CAS latency=2 CLK to valid output delay CAS latency=3 CAS latency=2 Output data hold time CAS latency=3 CAS latency=2 CLK high pulse width CLK low pulse width Input setup time wInwpwut.DhaotldaSthimeeet4U.com CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2 Symbol tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ 50 Min Max 5 1000 - - 4.5 -- 2- -- 2- 2- 1.5 - 1- 1- - 4.5 -- 60 Min Max 6 1000 10 -5 -6 2.5 - 3- 2.5 - 2.5 - 1.5 - 1- 1- -5 -6 75 Min Max 7.5 1000 10 - 5.4 -6 3- 3- 2.5 - 2.5 - 1.5 - 0.8 - 1- - 5.4 -6 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. 4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time tSH applies for address holde time, clock enable hold time, commend hold time and data hold time Unit Note ns 1 ns 1,2 ns 2 ns 3 ns 3 ns 3, 4 ns 3, 4 ns 2 ns DQ BUFFER OUTPUT DRIVE CHARACTERISTICS Parameter Output rise time Symbol trh Condition Measure in linear region : 1.2V ~ 1.8V Min 1.37 Typ Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 2.0 2.9 Notes : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to. 2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to. 3. Measured into 50pF only, use these values to characterize to. 4. All measurements done with respect to VSS. Max 4.37 3.8 5.6 5.0 Unit Volts/ns Volts/ns Volts/ns Volts/ns Notes 3 3 1,2 1,2 11 of 14 Rev. 1.1 February 2006 11 Page

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