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PDF ICS8745B Data sheet ( Hoja de datos )
| Número de pieza | ICS8745B | |
| Descripción | 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS8745Bwww.DataSheet4U.com
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
ICS
The ICS8745B is a highly versatile 1:5 LVDS Clock • 5 differential LVDS outputs designed to meet
Generator and a member of the HiPerClockS™ or exceed the requirements of ANSI TIA/EIA-644
HiPerClockS™ family of High Performance Clock Solutions from
ICS. The ICS8745B has a fully integrated PLL
• Selectable differential clock inputs
and can be configured as zero delay buffer, multi- • CLKx, nCLKx pairs can accept the following differential
plier or divider, and has an output frequency range of 31.25MHz input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
to 700MHz. The Reference Divider, Feedback Divider and
Output Divider are each programmable, thereby allowing for
• Output frequency range: 31.25MHz to 700MHz
the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, • Input frequency range: 31.25MHz to 700MHz
1:2, 1:4, 1:8.The external feedback allows the device to achieve
“zero delay” between the input clock and the output clocks. • VCO range: 250MHz to 700MHz
The PLL_SEL pin can be used to bypass the PLL for system • External feedback for “zero delay” clock regeneration
test and debug purposes. In bypass mode, the reference clock with configurable frequencies
is routed around the PLL and into the internal output dividers.
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 30ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: 25ps ± 125ps
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
SEL0
SEL1
SEL2
SEL3
MR
8745BY
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
0
Q2 32 31 30 29 28 27 26 25
nQ2
1 SEL0 1
24 Q3
Q3
nQ3
Q4
nQ4
SEL1
CLK0
nCLK0
CLK1
2
3
4
5
ICS8745B
23 nQ3
22 VDDO
21 Q2
20 nQ2
nCLK1 6
19 GND
CLK_SEL 7
18 Q1
MR 8
17 nQ1
9 10 11 12 13 14 15 16
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. B DECEMBER 2, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS8745Bwww.DataSheet4U.com
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VOD
Δ VOD
V
OS
Δ VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
320
1.05
Typical
440
0
1.2
Maximum
550
50
1.35
25
Units
mV
mV
V
mV
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
fIN
Parameter
Input Frequency
CLK0, nCLK0,
CLK1, nCLK1
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
31.25
Typical
Maximum
700
700
Units
MHz
MHz
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(Ø)
Output Frequency
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
PLL_SEL = 0V, f ≤ 700MHz
PLL_SEL = 3.3V
3.1
-100
3.4
25
700
3.7
150
tsk(o) Output Skew; NOTE 3, 5
35
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5, 6
30
tjit(θ) Phase Jitter; NOTE 4, 5, 6
±52
odc Output Duty Cycle
46 50 54
tL PLL Lock Time
tR / tF
Output Rise/Fall Time; NOTE 7
200
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback
input signal across all conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
1
700
Units
MHz
ns
ps
ps
ps
ps
%
ms
ps
8745BY
www.icst.com/products/hiperclocks.html
5
REV. B DECEMBER 2, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8745Bwww.DataSheet4U.com
1:5 DIFFERENTIAL-TO-LVDS
ZERO DELAY CLOCK GENERATOR
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have same
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
U1
Pin 1
R7 C16 C11
C5
C6
C4
GND
VDDO
VDD
VDDA
C1
C2
VIA
50 Ohm
Traces
8745BY
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8745B
www.icst.com/products/hiperclocks.html
11
REV. B DECEMBER 2, 2004
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ICS8745B.PDF ] | |
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