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PDF ICS87421I Data sheet ( Hoja de datos )
| Número de pieza | ICS87421I | |
| Descripción | DIFFERENTIAL-TO-LVDS CLOCK GENERATOR | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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÷1/÷2 DIFFERENTIAL-TO-LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87421I is a high performance ÷1/÷2
ICS Differential-to-LVDS Clock Generator and a mem-
HiPerClockS™ ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from IDT. The CLK, nCLK
pair can accept most standard differential input
levels. The ICS87421I is characterized to operate from a 3.3V
power supply. Guaranteed part-to-part skew characteristics
make the ICS87421I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
ICS87421I
FEATURES
• One differential LVDS output
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK
nCLK
MR
÷1 0
R ÷2 1
F_SEL
Q
nQ
PIN ASSIGNMENT
CLK
nCLK
MR
F_SEL
1
2
3
4
8 VDD
7Q
6 nQ
5 GND
ICS87421I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
IDT™ / ICS™ LVDS CLOCK GENERATOR
1 ICS87421AMI REV. A OCTOBER 3, 2007
1 page  
ICS87421I
÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
ADDITIVE PHASE JITTER
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The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz) = 0.17ps typical
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ LVDS CLOCK GENERATOR
5 ICS87421AMI REV. A OCTOBER 3, 2007
5 Page 
ICS87421I
÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
RELIABILITY INFORMATION
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TABLE 7. θ VS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA
θ by Velocity (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
96°C/W
1
87°C/W
TRANSISTOR COUNT
The transistor count for ICS87421I is: 417
2.5
82°C/W
IDT™ / ICS™ LVDS CLOCK GENERATOR
11 ICS87421AMI REV. A OCTOBER 3, 2007
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS87421I.PDF ] | |
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