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PDF ICS8741004I Data sheet ( Hoja de datos )

Número de pieza ICS8741004I
Descripción DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS JITTER ATTENUATOR
Fabricantes Integrated Device Technology 
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
ICS8741004I
General Description
The ICS8741004I is a high performance
ICS Differential-to-LVDS/0.7V Differential Jitter
HiPerClockS™ Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as
those found in desktop PCs, the PCI Express clocks
are generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS8741004I has 3 PLL bandwidth modes: 200kHz,
600kHz and 2MHz. The 200kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may be
attenuated. The 600kHz provides an intermediate bandwidth that
can easily track triangular spread profiles, while providing good
jitter attenuation. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles, but the jitter attenuation
will not be as good as the lower bandwidth modes. Because some
2.5Gb serdes have x20 multipliers while others have x25
multipliers, the ICS8741004I can be set for 1:1 mode or 5/4
multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
The ICS8741004I uses IDT’s 3rd Generation FemtoClock™
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI
Express add-in cards.
PLL Bandwidth
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
Features
Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
One differential clock input pair
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V operating supply
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
nQA1
QA1
VDDO
QA0
nQA0
MR
BW_SEL
nc
VDDA
F_SELA
VDD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24 nQB1
23 QB1
22 VDDO
21 QB0
20 nQB0
19 IREF
18 F_SELB
17 OEB
16 GND
15 GND
14 nCLK
13 CLK
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
1
ICS8741004BGI REV. B SEPTEMBER 27, 2007

1 page




ICS8741004I pdf
ICS8741004I
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
www.DataSheet4U.com
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
OEA, OEB, MR,
VIH Input High Voltage F_SELA, F_SELB
BW_SEL
OEA, OEB, MR,
VIL Input Low Voltage F_SELA, F_SELB
BW_SEL
2
VDD – 0.3
-0.3
-0.3
VIM Input Mid Voltage BW_SEL
VDD/2 – 0.1
F_SELA, F_SELB,
IIH Input High Current MR, BW_SEL
OEA, OEB
VDD = VIN = 3.465V
VDD = VIN = 3.465V
IIL
MR,
Input Low Current F_SELA, F_SELB,
VDD = 3.465V, VIN = 0V
-5
OEA, OEB, BW_SEL VDD = 3.465V, VIN = 0V
-150
Maximum
VDD + 0.3
VDD + 0.3
0.8
+0.3
VDD/2 + 0.1
150
5
Units
V
V
V
V
V
µA
µA
µA
µA
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
IIH
IIL
VPP
VCMR
Input High Current
CLK
nCLK
Input Low Current
CLK
nCLK
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 1
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V,
VIN = 0V
VDD = 3.465V,
VIN = 0V
-5
-150
0.15
GND + 0.5
NOTE 1: Common mode input voltage is defined as VIH.
Maximum
150
5
1.3
VDD – 0.85
Units
µA
µA
µA
µA
V
V
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
290
1.2
Typical
390
1.35
Maximum
490
50
1.5
50
Units
mV
mV
V
mV
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
5
ICS8741004BGI REV. B SEPTEMBER 27, 2007

5 Page





ICS8741004I arduino
ICS8741004I
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
PRELIMINARY
www.DataSheet4U.com
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kresistor can be used.
Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100across. If they are left floating, we
recommend that there is no trace attached.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100
differential transmission line environment, LVDS drivers require a
matched load termination of 100across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
LVDS Driver
3.3V
50
+
R1
100
50
100Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
11
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