PDF ICS874004 Data sheet ( Hoja de datos )

Número de pieza	ICS874004
Descripción	PCI EXPRESS JITTER ATTENUATOR
Fabricantes	Integrated Circuit Systems
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No Preview Available ! Integrated Circuit Systems, Inc. PRELIMINARY ICS874004www.DataSheet4U.com PCI EXPRESS™ JITTER ATTENUATOR GENERAL DESCRIPTION The ICS874004 is a high performance Differential- ICS to HCSL Jitter Attenuator designed for use in PCI HiPerClockS™ Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, highphase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874004 has 3 PLL bandwidth modes: 200KHz, 400KHz, and 800KHz. 200KHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. 400KHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. 800KHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5 Gb serdes have x20 multipliers while others have than x25 multipliers, the 874004 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pin. Features • (4) Differential LVDS output pairs • (1) Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 50ps (maximum) design target • 3.3V operating supply • 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature The ICS874004 uses ICS 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express™ add-in cards. PLL BANDWIDTH BW_SEL 0 = PLL Bandwidth: ~200KHz Float = PLL Bandwidth: ~400KHz (Default) 1 = PLL Bandwidth: ~800KHz BLOCK DIAGRAM OEA PU F_SEL PD BW_SEL Float 0 = ~200KHz Float = ~400KHz 1 = ~800KHz CLK PD nCLK PU FB_IN PD nFB_IN PU Phase VCO Detector 490-640MHz 0 ÷5 (default) 1 ÷4 MR PD OEB PU ÷5 FB_OUT nFB_OUT QA0 nQA0 QA1 nQA1 QB0 nQB0 QB1 nQB1 PIN ASSIGNMENT nQA0 nQB0 QB0 VDDO FB_OUT nFB_OUT MR BW_SEL VDDA F_SEL VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 QA0 2 3 VDDO 22 QA1 21 nQA1 20 QB1 19 nQB1 18 nFB_IN 17 FB_IN 16 OEB 15 GND 14 nCLK 13 CLK ICS874004 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 874004AG www.icst.com/products/hiperclocks.html REV. A JANUARY 21, 2005 1 1 page Integrated Circuit Systems, Inc. PRELIMINARY ICS874004www.DataSheet4U.com PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION 3.3V POWER SUPPLY + Float GND - LVDS SCOPE Qx nQx 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT nQAx, nQBx QAx, QBx tcycle n ➤ tcycle n+1 tjit(cc) = tcycle n –tcycle n+1 1000 Cycles ➤ VDD nCLK, nFB_IN CLK, FB_IN V PP GND Cross Points DIFFERENTIAL INPUT LEVEL nQAx, nQBx QAx, QBx Pulse Width t PERIOD odc = t PW t PERIOD V CMR CYCLE-TO-CYCLE JITTER Clock 20% Outputs 80% tR 80% tF VSW I N G 20% OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD VDD out DC Input LVDS out ➤ VOS/∆ VOS OUTPUT RISE/FALL TIME VDD DC Input LVDS OFFSET VOLTAGE SETUP out ➤ 100 VOD/∆ VOD out DIFFERENTIAL OUTPUT VOLTAGE SETUP 874004AG www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 21, 2005 5 Page

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