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PDF ICS874003-05 Data sheet ( Hoja de datos )
| Número de pieza | ICS874003-05 | |
| Descripción | PCI EXPRESS JITTER ATTENUATOR | |
| Fabricantes | Integrated Device Technology | |
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PCI Express™ Jitter Attenuator
ICS874003-05
DATASHEET
General Description
The ICS874003-05 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some PCI
Express systems, such as those found in desktop PCs, the PCI
Express clocks are generated from a low bandwidth, high phase
noise PLL frequency synthesizer. In these systems, a jitter
attenuator may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and from
the system board. The ICS874003-05 has a bandwidth of 6.2MHz
with <1dB peaking, easily meeting PCI Express Gen2 PLL
requirements.
The ICS874003-05 uses IDT’s 3rd Generation FemtoClock™ PLL
technology to achieve the lowest possible phase noise. The device is
packaged in a 20-Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
Features
• Three differential LVDS output pairs
• One differential clock input
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Input frequency range: 98MHz to 128MHz
• Output frequency range: 98MHz to 320MHz
• VCO range: 490MHz - 640MHz
• Supports PCI-Express Spread-Spectrum Clocking
• High PLL bandwidth allows for better input tracking
• PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
• 0°C to 70°C ambient operating temperature
• Full 3.3V operating supply
• Available in lead-free (RoHS 6) packages
F_SEL[2:0] Function Table
Inputs
F_SEL2 F_SEL1 F_SEL0
000
(default) (default) (default)
100
010
110
001
101
011
111
Outputs
QA[0:1],
nQA[0:1]
QB0, nQB0
÷2 ÷2
÷5 ÷2
÷4 ÷2
÷2 ÷4
÷2 ÷5
÷5 ÷4
÷4 ÷5
÷4 ÷4
Pin Assignment
QA1
VDDO
QA0
nQA0
MR
F_SEL0
nc
VDDA
F_SEL1
VDD
1
2
3
4
5
6
7
8
9
10
20 nQA1
19 VDDO
18 QB0
17 nQB0
16 F_SEL2
15 OEB
14 GND
13 nCLK
12 CLK
11 OEA
ICS874003-05
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
ICS874003BG-05 REVISION B MARCH 21, 2014
1
©2014 Integrated Device Technology, Inc.
1 page  
ICS874003-05 Data Sheet
PCI EXPRESS™JITTER ATTENUATOR
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
IIH
Input High
Current
CLK
nCLK
IIL
Input Low
Current
CLK
nCLK
VPP
Peak-to-Peak Voltage;
NOTE 1
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
-150
0.15
VCMR
Common Mode Input
Voltage; NOTE 1, 2
GND + 0.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
275
1.20
Typical
Typical
375
1.35
Maximum
150
5
1.3
Units
µA
µA
µA
µA
V
VDD – 0.85
V
Maximum
485
50
1.50
50
Units
mV
mV
V
mV
ICS874003BG-05 REVISION B MARCH 21, 2014
5
©2014 Integrated Device Technology, Inc.
5 Page 
ICS874003-05 Data Sheet
PCI EXPRESS™JITTER ATTENUATOR
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any transmission-
line reflection issues, the components should be surface mounted
and must be placed as close to the receiver as possible. IDT offers a
full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4A can be used with either
type of output structure. Figure 4B, which can also be used with both
output types, is an optional termination with center tap capacitance
to help filter common mode noise. The capacitor value should be
approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
ZO ZT
Figure 4A. Standard Termination
LVDS
ZT Receiver
LVDS
Driver
ZO ZT
Figure 4B. Optional Termination
LVDS Termination
ZT
2 LVDS
C ZT Receiver
2
ICS874003BG-05 REVISION B MARCH 21, 2014
11
©2014 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS874003-05.PDF ] | |
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