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PDF ICS874003-04 Data sheet ( Hoja de datos )
| Número de pieza | ICS874003-04 | |
| Descripción | PCI EXPRESS Jitter Attenuator | |
| Fabricantes | Integrated Device Technology | |
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PCI EXPRESS™ Jitter Attenuator
ICS874003-04
www.DataSheet4U.com
DATA SHEET
General Description
The ICS874003-04 is a high performance
ICS Differential-to-LVDS Jitter Attenuator designed for use
HiPerClockS™ in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the PCI
ExpressTM clocks are generated from a low bandwidth,
high phase noise PLL frequency synthesizer. In these systems, a
jitter attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer and
from the system board. The ICS874003-04 has a bandwidth of
6.8MHz. The 6.8MHz provides a high bandwidth that can easily track
triangular spread profiles, while providing jitter attenuation.
The ICS874003-04 uses IDT’s 3rd Generation FemtoClock™ PLL
technology to achieve the lowest possible phase noise. The device is
packaged in a 20 Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
Features
• Three differential LVDS output pairs
• One differential clock input
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Input frequency range: 98MHz to 128MHz
• Output frequency range: 98MHz to 320MHz
• VCO range: 490MHz - 640MHz
• Supports PCI-Express Spread-Spectrum Clocking
• High PLL bandwidth allows for better input tracking
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
F_SEL[2:0] Function Table
Inputs
F_SEL2 F_SEL1 F_SEL0
000
100
010
110
001
101
011
111
Outputs
QA[0:1], nQA[0:1] QB, nQB0
÷2 ÷2
÷5 ÷2
÷4 ÷2
÷2 ÷4
÷2 ÷5
÷5 ÷4
÷4 ÷5
÷4 ÷4
Pin Assignment
QA1
VDDO
QA0
nQA0
MR
F_SEL0
nc
VDDA
F_SEL1
VDD
1
2
3
4
5
6
7
8
9
10
20 nQA1
19 VDDO
18 QB0
17 nQB0
16 F_SEL2
15 OEB
14 GND
13 nCLK
12 CLK
11 OEA
ICS874003-04
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
ICS874003AG-04 REVISION A NOVEMBER 4, 2009
1
©2009 Integrated Device Technology, Inc.
1 page  
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
IIH
IIL
VPP
VCMR
Input High Current
CLK
nCLK
Input Low Current
CLK
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V,
VIN = 0V
VDD = 3.465V,
VIN = 0V
-5
-150
0.15
GND + 0.5
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
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Typical
Maximum
150
5
Units
µA
µA
µA
1.3
VDD – 0.85
µA
V
V
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
VOD
∆VOD
VOS
∆VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
275
1.20
Typical
375
1.35
Maximum
485
50
1.50
50
Units
mV
mV
V
mV
Table 5. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
fMAX
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
tsk(o)
Output Skew; NOTE 1, 2
tsk(b)
Bank Skew; NOTE 1, 3
Bank A
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Minimum
98
215
47
Typical
Maximum
320
35
135
50
550
53
Units
MHz
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
ICS874003AG-04 REVISION A NOVEMBER 4, 2009
5
©2009 Integrated Device Technology, Inc.
5 Page 
ICS874003-04 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Schematic Example
Figure 5 shows an example of ICS874003-04 application schematic.
In this example, the device is operated at VDD = 3.3V. The decoupling
capacitors should be located as close as possible to the power pin.
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Two examples of LVDS terminations are shown in this schematic.
The input is driven either by a 3.3V LVPECL driver or a 3.3V
LVCMOS.
ICS874003-04
Figure 5. ICS874003-04 Schematic Example
ICS874003AG-04 REVISION A NOVEMBER 4, 2009
11
©2009 Integrated Device Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet ICS874003-04.PDF ] | |
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