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PDF ICS874003-02 Data sheet ( Hoja de datos )

Número de pieza ICS874003-02
Descripción PCI EXPRESS JITTER ATTENUATOR
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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PCI EXPRESS™ JITTER ATTENUATOR
www.DataSheet4U.com
ICS874003-02
GENERAL DESCRIPTION
The ICS874003-02 is a high performance Dif-
ICS ferential-to-LVDS Jitter Attenuator designed for
HiPerClockS™ use in PCI Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS874003-02 has a bandwidth of 400kHz. The 400kHz
provides an intermediate bandwidth that can easily track
triangular spread profiles, while providing good jitter
attenuation.
The ICS874003-02 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
FEATURES
Three Differential LVDS output pairs
One Differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 320MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
Supports PCI-Express Spread-Spectrum Clocking
The 400kHz bandwidth mode allows the system designer to
make jitter attenuation/tracking skew design trade-offs
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
OEA Pullup
F_SEL2:0 Pulldown
3
CLK Pulldown
nCLK Pullup
Phase
Detector
VCO
490 - 640MHz
F_SEL[2:0] FUNCTION TABLE
F_SEL2
0
1
0
1
0
1
0
1
Inputs
F_SEL1
0
0
1
1
0
0
1
1
F_SEL0
0
0
0
0
1
1
1
1
Outputs
QA0/nQA0, QA0/nQA0
÷2
÷5
÷4
÷2
÷2
÷5
÷4
÷4
QB0/nQB0
÷2
÷2
÷2
÷4
÷5
÷4
÷5
÷4
÷5
÷4
÷2 (default)
3
QA0
nQA0
QA1
nQA1
PIN ASSIGNMENT
QA1
VDDO
QA0
nQA0
MR
F_SEL0
nc
VDDA
F_SEL1
VDD
1
2
3
4
5
6
7
8
9
10
20 nQA1
19 VDDO
18 QB0
17 nQB0
16 F_SEL2
15 OEB
14 GND
13 nCLK
12 CLK
11 OEA
MR Pulldown
OEB Pullup
M = ÷5 (fixed)
÷5
÷4
÷2 (default)
QB0 ICS874003-02
20-Lead TSSOP
nQB0
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR
1
ICS874003AG-02 REV A AUGUST 29, 2006

1 page




ICS874003-02 pdf
ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
www.DataSheet4U.com
3.3V±5%
POWER SUPPLY
+ Float GND –
VDD,
VDDO
VDDA
LVDS
SCOPE
Qx
nQx
VDD
nCLK
CLK
V
PP
GND
Cross Points
V
CMR
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQA0, nQA1,
nQB0
QA0, QA1,
QB0
tcycle n
tcycle n+1
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
nQx
Qx
nQy
Qy
t sk(o)
CYCLE-TO-CYCLE JITTER
nQXx
QXx
nQXy
QXy
t sk(b)
Where X = A or B
BANK SKEW
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR
OUTPUT SKEW
nQA0, nQA1,
nQB0
QA0, QA1,
QB0
t PW
t
PERIOD
odc = t PW x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
5 ICS874003AG-02 REV A AUGUST 29, 2006

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ICS874003-02 arduino
ICS874003-02
PCI EXPRESS™ JITTER ATTENUATOR
RELIABILITY INFORMATION
www.DataSheet4U.com
TABLE 6. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
114.5°C/W
73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS874003-02 is: 1408
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR
11
ICS874003AG-02 REV A AUGUST 29, 2006

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