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PDF M36L0T7050T2 Data sheet ( Hoja de datos )
| Número de pieza | M36L0T7050T2 | |
| Descripción | (M36L0T7050T2 / M36L0T7050B2) 128 Mbit Flash memory and 32 Mbit PSRAM | |
| Fabricantes | Numonyx | |
| Logotipo |  |
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M36L0T7050T2
M36L0T7050B2
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory
and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
Preliminary Data
Feature summary
■ Multi-Chip Package
– 1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-level, Burst) Flash Memory
– 1 die of 32 Mbit (2Mb x16) Pseudo SRAM
■ Supply voltage
– VDDF = 1.7 to 1.95V
– VCCP = VDDQ = 2.7 to 3.1V
– VPPF = 9V for fast program
■ Electronic signature
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration)
M36L0T7050T2: 88C4h
– Device Code (Bottom Flash Configuration)
M36L0T7050B2: 88C5h
■ ECOPACK® packages available
Flash memory
■ Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 52MHz
– Random Access: 85ns
■ Synchronous Burst Read Suspend
■ Programming time
– 2.5µs typical Word program time using
Buffer Enhanced Factory Program
command
■ Memory organization
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
■ Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
FBGA
TFBGA88 (ZAQ)
8 x 10mm
■ Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
■ Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
■ Common Flash Interface (CFI)
■ 100,000 program/erase cycles per block
PSRAM
■ Access time: 65ns
■ 8-Word Page Access capability: 18ns
■ Low standby current: 100µA
■ Deep power down current: 10µA
■ Compatible with standard LPSRAM
■ Power-down modes
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
November 2007
Rev 0.2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/22
www.numonyx.com
1
1 page  
M36L0T7050T2, M36L0T7050B2
List of figures
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Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch,
Bottom View Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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5 Page 
M36L0T7050T2, M36L0T7050B2
Siwgnwawl.DdaetsacShriepetti4oUn.csom
2.12
PSRAM Chip Enable Input (E2P)
The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low.
This is the lowest power mode.
2.13
2.14
PSRAM Write Enable (WP)
The Write Enable, WP, controls the Bus Write operation of the memory.
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write
cycles to be achieved with the common I/O data bus.
2.15
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
DQ15) to or from the upper part of the selected address during a Write or Read operation.
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
DQ7) to or from the lower part of the selected address during a Write or Read operation.
2.17
VDDF Supply Voltage
VDDF provides the power supply to the internal cores of the Flash memory component. It is
the main power supply for all Flash operations (Read, Program and Erase).
2.18
VCCP Supply Voltage
The VCCP Supply Voltage supplies the power for all operations (Read or Write) and for
driving the refresh logic, even when the device is not being accessed.
2.19
VDDQ Supply Voltage
VDDQ provides the power supply for the Flash memory I/O pins. This allows all Outputs to be
powered independently of the Flash Memory core power supply, VDDF.
11/22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M36L0T7050T2.PDF ] | |
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