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PDF M36L0T7050T0 Data sheet ( Hoja de datos )
| Número de pieza | M36L0T7050T0 | |
| Descripción | (M36L0T7050T0 / M36L0T7050B0) 128Mbit Flash Memory 32Mbit PSRAM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M36L0T7050T0
M36L0T7050B0
128Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory
32Mbit (2M x16) PSRAM, Multi-Chip Package
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 128Mbit (8Mx16, Multiple Bank,
Multi-level, Burst) Flash Memory
– 1 die of 32Mbit (2Mx16) Pseudo SRAM
■ SUPPLY VOLTAGE
– VDDF = 1.7 to 2V
– VDDP = VDDQ = 2.7 to 3.3V
– VPP = 9V for fast program (12V tolerant)
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration)
M36L0T7050T0: 88C4h
– Device Code (Bottom Flash
Configuration) M36L0T7050B0: 88C5h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 50MHz
– Asynchronous Page Read mode
– Random Access: 90ns
■ SYNCHRONOUS BURST READ SUSPEND
■ PROGRAMMING TIME
– 10µs typical Word program time using
Write to Buffer and Program
■ MEMORY ORGANIZATION
– Multiple Bank Memory Array: 8 Mbit
Banks
– Parameter Blocks (Top or Bottom
location)
■ DUAL OPERATIONS
– program/erase in one Bank while read in
others
– No delay between read and write
operations
■ SECURITY
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Figure 1. Package
FBGA
TFBGA88 (ZAQ)
8 x 10mm
■ BLOCK LOCKING
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
PSRAM
■ ACCESS TIME: 70ns
■ LOW STANDBY CURRENT: 100µA
■ DEEP POWER-DOWN CURRENT: 10µA
■ BYTE CONTROL: UBP/LBP
■ PROGRAMMABLE PARTIAL ARRAY
■ 8 WORD PAGE ACCESS CAPABILITY: 18ns
■ POWER-DOWN MODES
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
– 16 Mbit Partial Array Refresh
December 2004
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1 page  
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M36L0T7050T0, M36L0T7050B0
Figure 3. TFBGA Connections (Top view through package)
12345678
A DU DU
DU DU
B
A4
A18
A19
VSS VDDF
NC
A21 A11
C A5 LBP NC VSS NC KF A22 A12
D
A3 A17 NC VPPF WP EP
A9 A13
E
A2
A7
NC WPF LF
A20 A10 A15
F A1 A6 UBP RPF WF A8 A14 A16
G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAITF NC
H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC
J
NC
GF
DQ9 DQ11 DQ4
DQ6 DQ15 VDDQ
K
EF
DU
DU
NC
VDDP
NC
VDDQ
E2P
L VSS VSS VDDQ VDDF VSS VSS VSS VSS
M DU DU
DU DU
AI08735
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M36L0T7050T0, M36L0T7050B0
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Symbol
Parameter
Value
Min Max
Unit
TA Ambient Operating Temperature
–25
85 °C
TBIAS
Temperature Under Bias
–25 85 °C
TSTG
Storage Temperature
–55 125 °C
TLEAD
Lead Temperature during Soldering
(1) °C
VIO Input or Output Voltage
–0.5
3.6 V
VDDF
Flash Memory Core Supply Voltage
–0.2
2.5 V
VDDQ, VDDP
PSRAM and Input/Output Supply
Voltages
–0.2
3.6 V
VPPF
Flash Program Voltage
–0.2
14 V
IO Output Short Circuit Current
100 mA
tVPPFH
Time for VPPF at VPPFH
100 hours
Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification,
and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
11/18
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