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PDF SC905 Data sheet ( Hoja de datos )
| Número de pieza | SC905 | |
| Descripción | CDMA Cellular Phone Power Management IC | |
| Fabricantes | Semtech | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SC905 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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POWER MANAGEMENT
Description
The SC905 is a power management integrated circuit
(PMIC) designed for the latest CDMA chip sets. The device
provides four general purpose low dropout regulators
(LDOs), and five low noise LDOs designed for analog cir-
cuits. The VMOT LDO can be used as a general purpose
regulator or as an adjustable motor drive output that can
supply up to 150mA to drive a vibrator motor.
Each LDOs enable and output voltage are controlled via
the I2C bus. An optional three-wire interface compatible
with Semtech battery charger ICs is also controlled via the
I2C bus.
Initial power-on is achieved by activating either the ON or
the HFPWR signal, and the PGOOD input is used by the
microprocessor to latch power on or disable the device.
The small and thermally efficient MLPQ-32 package and
use of ceramic bypass capacitors, minimize the required
PCB area making the SC905 ideal for space-conscious
portable applications.
Typical Application Circuit
SC905
CDMA Cellular Phone
Power Managementwww.DataSheet4U.com IC
Features
9 LDO Linear Regulators
CORE: 1.35V - 2.90V @ 300mA
ANA: 2.55V - 2.90V @ 200mA
PAD: 1.35V - 2.90V @ 300mA
RX: 2.55V - 2.90V @ 150mA
TX: 2.55V - 2.90V @ 150mA
TCXO: 2.55V - 2.90V @ 80mA
PLL: 2.55V - 2.90V @ 80mA
Camera: 1.35V - 2.90V @ 100mA
Motor Drive: 1.35V - 2.90V @ 150mA
I2C Interface for Microprocessor Control
Less than 1μA Quiescent Current in Shutdown
65dB PSRR for Analog LDOs
Over-Temperature Protection
Power-On Control
Optional Interface for Controlling Semtech
Battery Chargers
Small 5mm x 5mm 32-Pin QFN Package
Applications
CDMA Cellular Handsets
Palmtop/Laptop Computers
Battery Powered Equipment
Battery
Charger
Circuit
ON/OFF
Handsfree
Option
MOTOR
SC905
CPB
CHRGB
FAULTB
VBAT
IN1
IN2
IN3
IN4
IN5
ON
HFPWR
PGOOD
SDA
SCL
PWRON
RESB
IN6
DVIN
VCORE
VPAD
VANA
VTCXO
VPLL
VTX
0.1μF
VMOT
BP
AGND
VRX
VCAM
VPSEL
VCSEL
DGND
VBAT
10μF
BATTERY
1μF
1μF
1μF 1μF
1μF
1μF
Baseband
Processor
1μF
1μF
Keypad
Audio
Processing
TCXO
+
Synthesiser
PLL
Transmitter
Section
PA
Receiver
Section
LNA
Camera
Module
Digital
Interface
June 7, 2006
1 www.semtech.com
1 page  
SC905
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Parameter
LDO Regulator (PLL) - 80mA
Symbol
Output Voltage Accuracy(4)
∆VOUT
Current Limit
Default At Start Up: OFF
Line Regulation
Load Regulation
Dropout Voltage
Power Supply Rejection Ratio
ILIM
VOUT
REGLINE
REGLOAD
VDO
PSRRPLL
Output Voltage Noise
en
LDO Regulator (MOT) - 150mA
Output Voltage Accuracy(3)
Current Limit
Default at Start Up: OFF
Line Regulation
Load Regulation
Dropout Voltage
Power Supply Rejection Ratio
∆VOUT
ILIM
VOUT
REGLINE
REGLOAD
VDO
PSRRMOT
Condition
2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA,
VOUT +0.35V ≤ VIN ≤ 5.5V
VPLL = 0V
IOUT = 1mA, VOUT +0.35V < VIN < 5.5V
1mA < IOUT < 80mA
VOUT = 2.90V, IOUT = 80mA
f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA
f = 10Hz - 100kHz, I OUT = 50mA,
CBP= 0.1μF, COUT = 1μF
1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA,
VOUT +0.35V ≤ VIN ≤ 5.5V
VMOT = 0V
IOUT = 1mA, VOUT +0.35V < VIN < 5.5V
1mA < IOUT < 150mA
VOUT = 2.90V, IOUT = 150mA
f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA
www.DataSheet4U.com
Min Typ Max
Units
-75 +75
250 650
2.85
2.5 12
-3 -20
200 250
65
45
mV
mA
V
mV
mV
mV
dB
μVRMS
-75 +75
250 650
1.40
2.5 12
-3 -20
200 250
50
mV
mA
V
mV
mV
mV
dB
© 2006 Semtech Corp.
5
www.semtech.com
5 Page 
SC905
POWER MANAGEMENT
Applications Information (Cont.)
The voltage can be changed from its default state after
start-up by writing to the appropriate voltage code regis-
ter.
Active Shutdown
The shutdown control bits determine how the on-chip active
shutdown switches behave. Register 7 is the active shut-
down control register and is used to control the shutdown
behavior. Each LDO has a specific shutdown bit assigned
to it. When the active shutdown bit is enabled (set to 1),
the output capacitance on the LDO output is discharged by
an on-chip FET when the LDO is disabled. When the active
shutdown bit is disabled (set to 0), the output capacitance
on the LDO output is discharged by the load. The default
state for each LDO active shutdown bit is on.
www.DataSheet4U.com
correct register information to the SC905 to set it to the
user state.
2) The MSM reads back all of the information to verify
the data. Then it reads back the DSB again to ensure it is
still set to 0. This verifies that no reset took place during
the time that the multiple writes and read verifications
happened. If the DSB has been reset to 1, this process
needs to be repeated since the chip was reset sometime
during the initialization. Once the MSM and the SC905
are synchronized, the DSB can be read back as a status
check periodically, as needed. If it is ever set back to the
default state, a new synchronization process is required.
This handshake-style protocol makes sure that the MSM
and SC905 are always synchronized.
Default Status Bit
In many multi-threaded environments it is necessary to
maintain synchronization between the host micro-control-
ler and the target IC. The SC905 has a default status bit
(DSB) that will facilitate this task. The DSB can be useful in
keeping the MSM and the SC905 synchronized. However,
this is only useful if the MSM is powered by an external
switching regulator such as the SC190.
The DSB is bit 7 of register 0, and shares this register space
with the PAD voltage control bits. The DSB is only set to 1
during power-up to indicate that the part is set to the default
state. Moreover, the DSB cannot be written to a 1 through
the I2C interface the way the other bits in this register can;
it can only be cleared to 0 through the I2C interface. This
feature prevents a software race condition by always writing
to register 0 with bit 7 high when changing the PAD control
voltage. To clear the bit simply write a 0 to bit 7.
Applying the DSB
Upon power-up, the SC905 LDOs and internal registers are
set to their default state. The DSB is set to a 1 to indicate
that the SC905 is in its default state. Upon reading this
defaulted state condition, the MSM knows to perform
whatever synchronization is needed to set the SC905 into
a known user state. This user state is entered by a two-
stage process.
1) The MSM writes a 0 to the DSB indicating its desire
to modify the state of the SC905. It then writes all of the
LDO Power-On Sequence
When the SC905 first turns on, the four LDOs that default
on are sequenced in the following fashion: CORE is the first
to turn on, then PAD, then ANA and finally TCXO. During the
power-on sequence, each LDO has a 100μs delay from one
LDO turning on to the other. This process eliminates large
voltage spikes across the battery supply during power-up.
For further information on LDO power on sequencing, refer
to the Timing Diagram on page 17.
Protection Circuitry
The SC905 contains protection circuitry that prevents the
device from operating in an unspecified state. These in-
clude Under-voltage Lockout Protection, Over-temperature
Protection and Short-circuit Protection.
Under-Voltage Lockout
The SC905 provides an under-voltage lockout (UVLO) circuit
to protect the device from operating in an unknown state
if the input voltage supply is too low.
When the battery voltage drops below the UVLO threshold,
as defined in the Electrical Characteristics section, the
LDOs are disabled and RESB is held low. When the battery
voltage is increased above the hysteresis level, the LDOs
are re-enabled into their previous states, provided PGOOD
has remained high. If PGOOD goes low, the SC905 will shut
down. When powering-up with a battery voltage below the
UVLO threshold, RESB will be held low.
© 2006 Semtech Corp.
11
www.semtech.com
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet SC905.PDF ] | |
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