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PDF W3HG128M64EEU-D4 Data sheet ( Hoja de datos )

Número de pieza W3HG128M64EEU-D4
Descripción 1GB - 128Mx64 DDR2 SDRAM UNBUFFERED
Fabricantes White Electronic Designs 
Logotipo White Electronic Designs Logotipo



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No Preview Available ! W3HG128M64EEU-D4 Hoja de datos, Descripción, Manual

White Electronic Designs
W3HG128M64EEU-D4
www.DataSheet4UA.cDoVmANCED*
1GB – 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
FEATURES
200-pin, Small-Outline DIMM (SO-DIMM), Raw
Card "B"
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
VCC = VCCQ = 1.8V ± 0.1V
VCCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-Die Termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Single Rank
RoHS Compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 29.20mm (1.150") TYP
DESCRIPTION
The W3HG128M64EEU is a 128Mx64 Double Data Rate
2 SDRAM memory module based on 1Gb DDR2 SDRAM
components. The module consists of eight 128Mx8, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
PC2-6400*
400MHz
6-6-6
OPERATING FREQUENCIES
PC2-5300*
333MHz
5-5-5
PC2-4200
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
March 2006
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3HG128M64EEU-D4 pdf
White Electronic Designs
W3HG128M64EEU-D4
www.DataSheet4U.AcDomVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
DDR2 SDRAM components only
VCC = +1.8V ± 0.1V
Parameter
Symbol Condition
806
Operating one device
bank active-precharge
current;
tCK = tCK (ICC), tRC = tRC (ICC), tRAS = tRAS MIN (ICC); CKE is HIGH, CS# is
ICC0 HIGH between valid commands; Address bus inputs are SWITCHING; TBD
Data bus inputs are SWITCHING.
Operating one device
bank active-read-
precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK (ICC), tRC = tRC (ICC),
ICC1
tRAS = tRAS MIN (ICC), tRCD = tRCD (ICC); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data
pattern is same as ICC4W.
Precharge power-down
current;
ICC2P
All device banks idle; tCK = tCK (ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
TBD
TBD
Precharge quiet
standby current;
Precharge standby
current;
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
ICC2Q control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
All device banks idle; tCK = tCK (ICC); CKE is HIGH, CS# is HIGH; Other
ICC2N control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
TBD
TBD
Active power-down
current;
All device banks open; tCK = tCK (ICC); CKE is LOW;
ICC3P Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
TBD
TBD
All device banks open; tCK = tCK(ICC), tRAS = tRAS MAX (ICC), tRP = tRP(ICC);
Active standby current; ICC3N CKE is HIGH, CS# is HIGH between valid commands; Other control and TBD
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst write
current;
ICC4W
All device banks open, Continuous burst writes; BL = 4, CL = CL (ICC),
AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
TBD
Operating burst read
current;
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL
ICC4R
= CL (ICC), AL = 0; tCK = tCK (ICC), tRAS = tRAS MAX (ICC), tRP = tRP (ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
Burst refresh current;
tCK = tCK (ICC); Refresh command at every tRFC (ICC) interval; CKE
ICC5 is HIGH, CS# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
TBD
Self refresh current;
ICC6
CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING.
TBD
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (ICC),
Operating device bank
interleave read current;
ICC7
AL = tRCD (ICC)-1 x tCK (ICC); tCK = tCK (ICC), tRC = tRC(ICC), tRRD = tRRD(ICC),
tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs
TBD
are SWITCHING
Note:
• ICC specification is based on MICRON components. Other DRAM manufacturers specification may be different.
665
800
1,160
56
480
520
320
80
560
1,440
1,640
2,160
56
2,720
534 403 Units
640 640 mA
760 760 mA
40 40 mA
328 280 mA
360 280 mA
240 200 mA
80 80 mA
400 320 mA
1,040 960 mA
1,160 1,080 mA
2,000 1,920 mA
40 40 mA
2,360 2,360 mA
March 2006
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3HG128M64EEU-D4 arduino
White Electronic Designs
W3HG128M64EEU-D4
www.DataSheet4UA.cDoVmANCED*
tCKAVG(MIN) is the smallest clock rate allowed, except a deviation due to allowed
clock jitter. Input clock jitter is allowed provided it does not exceed values specified.
Also, the jitter must be of a random Gaussian distribution in nature.
37. The inputs to the DRAM must be aligned to the associated clock; that is, the actual
clock that latches it in. However, the input timing (in ns) references to the tCKAVG
when determining the required number of clocks. The following input parameters are
determined by taking the specified percentage times the tCKAVG rather thank tCK:
tIPW, tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDH, tWPST, and tWPRE.
38. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz
with additional one percent of tCKAVG as a long-term jitter component; however,
the spread spectrum may not use a clock rate below tCKAVG(MIN) or above
tCKAVG(MAX).
39. The period jitter (tJITPER) is the maximum deviation in the clock period from the
average or nominal clock allowed in either the positive or negative direction. JEDEC
specifies tighter jitter numbers during DLL locking time. During DLL lock time, the
jitter values should be 20 percent less than noted in the table (DLL locked).
40. The half-period jitter (tJITDTY) applies to either the high pulse of clock or the low
pulse of clock; however, the two cumulatively can not exceed tJITPER.
41. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from
one cycle to the following cycle. JEDEC specifies tighter jitter numbers during DLL
locking time. During DLL lock time, the jitter values should be 20 percent less than
noted in the table (DLL locked).
42. The cumulative jitter error (tERRnPER) where n is 2, 3, 4, 5, 6–10, or 11–50, is the
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
43. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting tERR5PER(MAX): tAC(MIN), tDQSCK(MIN),
tHZ(MIN), tLZDQ(MIN), tAON(MIN); while these following parameters are required
to be derated by subtracting tERR5PER(MIN): tAC(MAX), tDQSCK(MAX), tHZ(MAX),
tLZDQ(MAX), tAON(MAX). The parameter tRPRE(MIN) is derated by subtracting
tJITPER(MAX), while tPRPE(MAX), is derated by subtracting tJITPER(MAX) . The
parameter tRPST(MAX), is dated by subtracting tJITDTY(MIN).
44. Half-clock output parameters must be derated by the actual tERR5PER and tJITDTY
when input clock jitter is present; this will result in each parameter becoming
larger. The parameter tAOF(MIN) is required to be derated by subtracting both
tERR5PER(MAX) and tJITPER(MAX). The parameter tAOF(MAX) is required to be
derated by subtracting both tERR5PER(MIN) and tJITDTY(MIN).
45. MIN(tCL, tCH) refers to the smaller of the actual clock LOW time and the actual
clock HIGH time driven to the device. The clock's half period must also be of a
Gaussian distribution; tCHAVG and tCLAVG must be met with or with our clock jitter
and with or without duty cycle jitter. tCHAVG and tCLAVG are the average of any 200
consecutive CK falling edges.
46. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK#
inputs; thus, tHP(MIN) ≥ the lesser of tCLABS(MIN) and tCHABS(MIN).
47. tQH = tHP - tQHS; the worst case tQH would be the smaller of tCLABS(MAX) or
tCHABS(MAX) times tCKABS(MIN) - tQHS. Minimizing the amount of tCHAVG offset and
value of tJITDTY will provide a larger tQH, which in turn will provide a larger valid data
out window.
48. JEDEC specifies using tERR6-10PER when derating clock-related output timing (notes
43–44). Micron requires less derating by allowing tERR5PER to be used.
49. Requires 8 tCK for backward compatibility.
March 2006
Rev. 0
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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