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PDF W3H64M72E-XSBX Data sheet ( Hoja de datos )

Número de pieza W3H64M72E-XSBX
Descripción 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Fabricantes White Electronic Designs 
Logotipo White Electronic Designs Logotipo



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No Preview Available ! W3H64M72E-XSBX Hoja de datos, Descripción, Manual

White Electronic Designs
W3H64M72E-XSBX
www.DataSheet4UA.cDoVmANCED*
64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667*, 533, 400
Programmable CAS latency: 3, 4 or 5
Package:
Posted CAS additive latency: 0, 1, 2, 3 or 4
• 208 Plastic Ball Grid Array (PBGA), 17 x 23mm
Write latency = Read latency - 1* tCK
• 1.0mm pitch
DDR2 Data Rate = 667*, 533, 400
Core Supply Voltage = 1.8V ± 0.1V
I/O Supply Voltage = 1.8V ± 0.1V - (SSTL_18
compatible)
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature
Ranges
Organized as 64M x 72
Weight: W3H64M72E-XSBX - 2.5 grams typical
BENEFITS
63% SPACE SAVINGS vs. FPBGA
Reduced part count
55% I/O reduction vs FPBGA
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 128M x 72 density (contact factory
for information)
On Die Termination (ODT)
Adjustable data – output drive strength
* This product is under development, is not qualified or characterized and is subject
to change or cancellation without notice.
11.0
19.0 90
FBGA
FIGURE 1 – DENSITY COMPARISONS
CSP Approach (mm)
11.0 11.0 11.0
11.0
90
FBGA
90
FBGA
90
FBGA
90
FBGA
Actual Size
W3H64M72E-XSBX
White Electronic Designs
W3H64M72E-XSBX
23
17
S
A
V
I
N
G
S
Area
I/O
Count
5 x 209mm2 = 1,045mm2
5 x 92 balls = 460 balls
391mm2
208 Balls
63%
55%
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W3H64M72E-XSBX pdf
White Electronic Designs
W3H64M72E-XSBX
www.DataSheet4UA.cDoVmANCED*
A0-A12
DQ0-71
UDQS, UDQS#
LDQS, LDQS#
VCC
VCCQ
VREF
VSS
NC
DNU
Input
I/O
I/O
I/O
Supply
Supply
Supply
Supply
-
-
TABLE – 1 BALL DESCRIPTIONS (continued)
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
Power Supply: 1.8V ±0.1V
DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved noise immunity
SSTL_18 reference voltage.
Ground
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W3H64M72E-XSBX arduino
White Electronic Designs
W3H64M72E-XSBX
www.DataSheet4UA.cDoVmANCED*
CAS LATENCY (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of
the first bit of output data. The CL can be set to 3, 4, 5,
or 6 clocks, depending on the speed grade option being
used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AL). This feature allows the READ
command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
Examples of CL = 3 and CL = 4 are shown in Figure 6;
both assume AL = 0. If a READ command is registered
at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n+m (this
assumes AL = 0).
CK#
CK
COMMAND
DQS, DQS#
DQ
T0
READ
FIGURE 6 – CAS LATENCY (CL)
T1 T2 T3 T4
NOP
NOP
NOP
NOP
T5
NOP
CL = 3 (AL = 0)
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T6
NOP
CK#
CK
COMMAND
DQS, DQS#
DQ
T0
READ
T1 T2
NOP
NOP
CL = 4 (AL = 0)
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal t AC, t DQSCK, and t DQSQ
T3
NOP
T4 T5 T6
NOP
NOP
NOP
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
TRANSITIONING DATA
DON’T CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

11 Page







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