DataSheet.es    


PDF IDT72V7270 Data sheet ( Hoja de datos )

Número de pieza IDT72V7270
Descripción (8192 x 72)3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



Hay una vista previa y un enlace de descarga de IDT72V7270 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! IDT72V7270 Hoja de datos, Descripción, Manual

3.3 VOLT HIGH-DENSITY SUPERSYNC II™ 72-BIT FIFO
512 x 72, 1,024 x 72
2,048 x 72, 4,096 x 72
8,192 x 72, 16,384 x 72
32,768 x 72, 65,536 x 72
IDwTw7w2.VD7a2ta3S0h,eIeDtT4U7.2cVom7240
IDT72V7250, IDT72V7260
IDT72V7270, IDT72V7280
IDT72V7290, IDT72V72100
FEATURES:
Choose among the following memory organizations:
IDT72V7230 512 x 72
IDT72V7240 1,024 x 72
IDT72V7250 2,048 x 72
IDT72V7260 4,096 x 72
IDT72V7270 8,192 x 72
IDT72V7280 16,384 x 72
IDT72V7290 32,768 x 72
IDT72V72100 65,536 x 72
100 MHz operation (10 ns read/write cycle time)
User selectable input and output port bus-sizing
- x72 in to x72 out
- x72 in to x36 out
- x72 in to x18 out
- x36 in to x72 out
- x18 in to x72 out
Big-Endian/Little-Endian user selectable word representation
Fixed, low first word latency
Zero latency retransmit
Auto power down minimizes standby power consumption
FUNCTIONAL BLOCK DIAGRAM
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Asynchronous operation of Output Enable, OE
Read Chip Select ( RCS ) on Read Side
Available in a 256-pin Fine Pitch Ball Grid Array package (PBGA)
Features JTAG (Boundary Scan)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
WEN WCLK
D0 -Dn (x72, x36 or x18)
LD SEN SCLK
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
BE
IP
BM
IW
OW
MRS
PRS
TCK
TRST
TMS
TDO
TDI
WRITE POINTER
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
JTAG
CONTROL
(BOUNDARY SCAN)
RAM ARRAY
512 x 72
1,024 x 72
2,048 x 72
4,096 x 72
8,192 x 72
16,384 x 72
32,768 x 72
65,536 x 72
OUTPUT REGISTER
OE
Q0 -Qn (x72, x36 or x18)
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
RCS
4680 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DECEMBER 2003
DSC-4680/9

1 page




IDT72V7270 pdf
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
Name
D0–D71 DataInputs
MRS MasterReset
PRS PartialReset
RT Retransmit
FWFT/SI
OW
IW
BM
First Word Fall
Through/Serial In
OutputWidth
Input Width
Bus-Matching
BE Big-Endian/
Little-Endian
RM RetransmitTiming
Mode
PFM Programmable
Flag Mode
IP Interspersed Parity
FSEL0 Flag Select Bit 0
FSEL1 Flag Select Bit 1
WCLK WriteClock
WEN
RCLK
Write Enable
Read Clock
REN Read Enable
OE OutputEnable
RCS Read Chip Select
SCLK
SEN
LD
Serial Input Clock
Serial Enable
Load
FF/IR
Full Flag/
Input Ready
www.DataSheet4U.com
I/O Description
I Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins should be tied
LOW.
I MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringMasterReset,
the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight
programmable flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian
format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable
flag timing modes.
I PRS initializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringPartialReset,
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or
programmable flag settings. RT is useful to reread data from the first physical location of the FIFO.
I DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
as a serial input for loading offset registers.
I This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
I This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
I BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
configuration.
I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
will select Little-Endian format.
I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
normal latency mode.
I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
PFM will select Synchronous Programmable flag timing mode.
I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
Parity mode.
I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
I When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable
registers for parallel programming.
I WEN enables WCLK for writing data into the FIFO memory and offset registers.
I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the
programmable registers. (RCS must be active).
I REN enables RCLK for reading data from the FIFO memory and offset registers. (RCS must be active).
I OE provides asynchronous control of the output impedance of Qn. During a Master or Partial Reset the OE
input is the only input that provide High-Impedance control of the data outputs.
I RCS providessynchronouscontrolof thereadportandoutputimpedanceofQn,synchronoustoRCLK.During
a Master or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
I when enabled by SEN, the rising edge of SCLK writes one bit of data (present on the SI input), into the
programmable register for serial programming.
I SEN enables serial loading of programmable flag offsets.
I This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
determines one of eight default offset values for the PAEandPAF flags, along with the method by which these
offsetregisterscanbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,thispinenableswriting
to and reading from the offset registers.
O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full.
In the FWFT mode, the IRfunction is selected. IRindicates whether or not there is space available for writing
to the FIFO memory.
5

5 Page





IDT72V7270 arduino
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
COMMERCIALTEMPERATURERANGE
www.DataSheet4U.com
11

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet IDT72V7270.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IDT72V7270(8192 x 72)3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFOIntegrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar