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PDF LF3312 Data sheet ( Hoja de datos )
| Número de pieza | LF3312 | |
| Descripción | 12-Mbit Frame Buffer / FIFO | |
| Fabricantes | LOGIC Devices | |
| Logotipo |  |
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DEVICES INCORPORATED
LF3312
12-MbitwFwrwa.mDaetaSBhueeftf4eUr.c/omFIFO
Preliminary Datasheet
Features
12,441,600-bit Frame Memory
74.25MHz Max Data Rate
May be Organized Into the Following
Configurations:
• 1,555,200 x 8-bit (single channel)
• 1,244,160 x 10-bit (single channel)
• 1,036,800 x 12-bit (single channel)
• 777,600 x 16-bit (width expansion - dual channel)
• 622,080 x 20-bit (width expansion - dual channel)
• 518,400 x 24-bit (width expansion - dual channel)
• 777,600 x 8-bit (each of two parallel channels)
• 622,080 x 10-bit (each of two parallel channels)
• 518,400 x 12-bit (each of two parallel channels)
Operating Modes:
• Random Access with External Address Port
(Single-channel)
• FIFO With Asynchronous I/O (Single-channel)
• FIFO With Asynchronous I/O (Dual-channel)
• Synchronous Shift Register (Single-channel)
• Synchronous Shift Register (Dual-channel)
• FIFO + shift register; Channel B Synchronized to
Channel A
• Shift register + FIFO; One channel Synchronized
to the other
Near-Full/Empty Flags With Programmable
Thresholds
Flexible Pointer Manipulation
• Write and Read Pointers may be indepen-
dently jumped to arbitrary address locations
• Write or Read Pointers can be manipulated
in real-time based on external 24bit address
LF3312s may be Cascaded for depth and
width, supporting HDTV, Multiframe SDTV,
and other high resolution formats
• Seamless address space is maintained
with up to 16 cascaded devices
Built-in ITU-R BT.656 TRS detection and
Synchronization
Set & Clear Read/Write Pointer Control Pins
Choice of Control Interfaces:
• Two-wire Serial Microprocessor Interface
• Parallel Microprocessor Interface
Input Enable Control (Write Mask) for freeze-
frame applications
Output Enable Control (Data Skipping)
JTAG Boundary Scan - IEEE 1149.1
172 ball LBGA package
1.8V Internal Core Power Supply
3.3V I/O Supply
NOTE: This Preliminary Datasheet references LF3312BGC Engineering Samples
with an ES marking under the part designation.
Applications
DTV/HDTV Video Stream Buffer
Frame Synchronization
CCTV Security Camera Systems
Time Base Correction (TBC)
Freeze-Frame Buffer
Regional Read/Write for Picture-in-Picture (PIP)
Field-Based or Frame-Based Comb Filtering
Video Capture & Editing Systems
Deep Data Buffering
Video Special Effects (Rotation, Zoom)
Test Pattern Generation
Motion Detection or Frame-to-Frame Correlation
LOGIC Devices Incorporated
Video Imaging Product
1 August 8, 2006 LDS.3312 O
1 page  
DEVICES INCORPORATED
LF3312
12-Mbit Frawmwwe.DBautafSfheeret/4UF.cIFomO
Preliminary Datasheet
Operating Modes
Asynchronous single-channel FIFO mode (OPMODE = 3)
In OPMODE 3, the LF3312 is configured as a single channel First-In-First-Out 12Mbit memory, with
independent read and write clocks to allow for asynchronous operation. This mode is ideal for buffering or
burst data applications. Arbitrary write/read pointer jumping is supported in all FIFO modes. In this mode
the device can re-time a data stream according to a read sync signal (RSET or RCLR) and either ITU-R656
Timing Reference Signals (TRS) embedded within the incoming (video) data or the falling edge of a write
sync signal applied to ACLR, ASET, or AMARK.
As a single channel FIFO, the LF3312 must have AWCLK and BWCLK tied together as must be AWEN
with BWEN, and AIEN with BIEN. The input (write) and output (read) clocks need not be synchronous with
one another, although the memory core will eventually fill or empty if they differ in average frequency. After
it “fills,” the LF3312 continues writing and the oldest data gets written over. If the memory core “empties”
(and neither the read nor write pointer have been set or cleared during run-time) the read pointer stops
incrementing, and the device re-reads the last written sample until more data is written. In either case,
when the read and write addresses reach equality, the ACOLLIDE flag will go high, to alert the host. The
almost-full and almost-empty flags provide advance warning of these conditions whenever user-selected
“fullness” or “emptiness” thresholds, expressed in approximate eightieths of the memory core size, are
exceeded. For example, if the 1/80 and 79/80 thresholds are enabled, flag APE will go HIGH whenever the
read pointer lags behind the write pointer by less than 1/80 of the memory space, and flag APF will go HIGH
whenever the read pointer leads the write pointer by this amount. (Calculations are performed modulo the
total address space.) The data input and output are sequential and the timing between write and read sync
signals dynamically determines the effective delay (depth) of the FIFO.
The ‘stop reading when empty’ FIFO-mode behavior can be avoided by making sure LOAD is HIGH and
issuing any write or read pointer SET or CLR command at any time. This effectively gets the device out
of this ‘read-pointer-halting’ mode from that point onwards, but invalidates the flags. Random Access Mode
allows free manipulation of the r/w pointers, and never halts the read pointer without being commanded
to do so using AREN or BREN. Since Random Access mode naturally increments the r/w pointers
sequentially, like in FIFO mode, it may be a better mode to use if pointer manipulation of a single-channel
of memory is desired.
Dual-channel asynchronous FIFO mode (OPMODE = 7; power-on default)
OPMODE 7 operates identically to the single channel FIFO (OPMODE 3), with two independent chanels.
In dual-channel asynchronous FIFO mode, the device can accept two asynchronous data streams and
automatically adjust the latency of each to bring it into alignment with an output sync signal applied to RSET
or RCLR. Again, the user may reference input synchronization either to ACLR, ASET, BCLR, and BSET,
to AMARK and BMARK, or to embedded TRS. The data read/output clock need not be synchronous with
either of the two input clocks, which likewise need not be synchronous with one another. If memory core
A or B “empties“ or “fills“ completely, ACOLLIDE and/or BCOLLIDE respectively, will be set accordingly if
the write and read pointers collide.
The data Word that BMARK ‘marks’ (by going LOW during that xWCLK cycle) in the input data stream
will be the first synchronized AOUT/BOUT data word. If N full frames of Channel A data have been
loaded into AIN before the first Channel B data frame is loaded into BIN, the second frame of B channel
data will be synchronized to the (N+1)th Channel A frame. (there will be N frames difference between
Channel A and B).
LOGIC Devices Incorporated
Video Imaging Product
5 August 8, 2006 LDS.3312 O
5 Page 
DEVICES INCORPORATED
LF3312
12-MbitwFwrwa.mDaetaSBhueeftf4eUr.c/omFIFO
Preliminary Datasheet
Parallel
Interface
Cont’d
Device Configuration
Figure 5 - Normal Reading and Writing From a Control Register
PCEx
PWE
PRE
PADDR[5:0]
PDATA[7:0]
tCSU
tCSU
tCSU
Read Cycle - Normal Mode
tCSPW
tCDLY
tCZ
PCEx
PWE
PRE
PADDR[5:0]
PDATA[7:0]
tCSU
tCSU
tCSU
Write Cycle - Normal Mode
tCSPW
tCSU tCHD
Figure 6 - Reading and Writing From a Control Register with REB Held Low
PCEx
PWE
PADDR[5:0]
PDATA[7:0]
Read Cycle - PRE held low
tCSPW
tCSU
tCDLY
tCZ
PCEx
PWE
PADDR[5:0]
PDATA[7:0]
Write Cycle - PRE held low
tCSPW
tCSU
tCSU tCHD
LOGIC Devices Incorporated
Video Imaging Product
11 August 8, 2006 LDS.3312 O
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LF3312.PDF ] | |
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