PDF LF3321 Data sheet ( Hoja de datos )

Número de pieza	LF3321
Descripción	Horizontal Digital Image Filter
Fabricantes	LOGIC Devices
Logotipo
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No Preview Available ! DEVICES INCORPORATED LF3321 Horizontawl wDwig.DiattaalShImeeat4gU.ecoFmilter Improved Performance FEATURES 111 MHz Data Rate 12-bit Data or Coefficients (Expandable to 24-bit) 32-Tap FIR Filter, Cascadable for More Filter Taps LF Interface™ Allows All 256 Coefficient Sets to be Updated Within Vertical Blanking Over 49 K-bits of on-board Memory Various Operating Modes: Dual Filter, Single Filter, Double Wide Data or Coefficient, Matrix Multiplica- tion, and Accumulator Access. Selectable 16-bit Data Output with User-Defined Rounding and Limiting Supports Interleaved Data Streams Supports Decimation up to 16:1 for Increas- ing Number of Filter Taps 3.3 Volt Power Supply 144 Lead PQFP DESCRIPTION The LF3321 is an improved version of the LF3320 Horizontal Digital Image Filter capable of operating at speeds of up to 111MHz. This improved speed increases flexibility and performance and enables the user to utilize this device in more applications. For example, four interleaved data streams of 27MHz can now be processed within one device. The part is functionally identical to the LF3320 with the exception that the filter data path is specified to operate faster than the LF Control Interface. When operating the filter at speeds in excess of 90MHz, loading of coefficients via the LF Interface must be throttled to a maximum of 90MHz by asserting the PAUSE pin as required to allow sufficient setup time for the configuration data provided to the chip via the LF Interface. Figure 1. Switching Waveforms: LF InterfaceTM CLK LDA LDB PAUSEA PAUSEB CFA 11-0 CFB 11-0 tS0 tCFH tCFS ADDRESS tPS tPWL tPWH tCYC tPH CF0 tLH CF1 Figure 1 demonstrates the switching waveforms, while the switching characteristics are given in Table 1. The LF3321 filters digital images in the horizontal dimension at real-time video rates. The input and coefficient data are both 12 bits and in two’s complement format. The output is also in two’s complement format and may be rounded to 16 bits. The LF3321 is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets are used, the device can be configured as a single 32-tap FIR filter or as two separate 16-tap FIR filters. When asymmetric coefficient sets are used, the device can be configured as a single 16-tap FIR filter or as two separate 8-tap FIR filters. Multiple LF3321s can be cascaded to create larger filters. Interleave/Decimation Registers (I/D Registers) allow interleaved data to be fed directly into the device and filtered without separating the data into individual data streams. The LF3321 can handle a maximum of sixteen data sets interleaved together. The I/D Registers and on-chip accumulators facilitate using decimation to increase the number of filter taps. Decimation of up to 16:1 is supported. The LF3321 contains enough on-board memory to store 256 coefficient sets. Two separate LF InterfacesTM allow all 256 coefficient sets to be updated within vertical blanking. LOGIC Devices Incorporated Video Imaging Products 1 Feb 5, 2003 LDS.3321-A 1 page DEVICES INCORPORATED Functional Description Figure 5. I/D Register Data Paths LF3321 Horizontawl wDwig.DiattaalShImeeat4gU.ecoFmilter Improved Performance A ALU B A ALU B A ALU B A ALU B Delay Stage N 1 Delay Stage N A ALU B A ALU B COEF 7 COEF 6 COEF 7 2 COEF 6 COEF 7 2 COEF 6 Data Reversal EVEN-TAP MODE ODD-TAP MODE ODD-TAP INTERLEAVE MODE When interleaved data is fed through the device and an even tap filter is desired, the filter should be configured for an even number of taps and the I/D Register length should match the number of data sets interleaved together. When interleaved data is fed through the device and an odd tap filter is desired, the filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration Register 1 and Configuration Register 3 configures Filters A and B respectively for Odd-Tap Interleave Mode. When the filter is configured for Odd-Tap Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the first I/D Register in the reverse data path. When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in the forward data path. In order to achieve the correct result, the user must divide the coefficient by two. Data reversal circuitry is placed after the multiplexers which route data from the forward data path to the reverse data path (see Figure 6). When decimating, the data stream must be reversed in order for data to be properly aligned at the inputs of the ALUs. Figure 6. Data Reversal LOGIC Devices Incorporated Video Imaging Products 5 Feb 5, 2003 LDS.3321-A 5 Page DEVICES INCORPORATED LF3321 Horizontawl wDwig.DiattaalShImeeat4gU.ecoFmilter Improved Performance LF Interface ™ Functional Description Table 7. Configuration Register 5 - Adress 205H BITS 0 1 11-2 FUNCTION Vertical Limit Enable Horizontal Limit Enable Reserved DESCRIPTION 0 : Vertical Limiting Disabled 1 : Vertical Limiting Enabled 0 : Horizontal Limiting Disabled 1 : Horizontal Limiting Enabled Must be set to “0” Table 8. CFA/CFB11-9 Decode 11 10 9 DESCRIPTION 0 0 0 Coefficient Banks 0 0 1 Configuration Registers 0 1 0 Filter A Select Registers 0 1 1 Filter B Select Registers 1 0 0 Filter A Round Registers 1 0 1 Filter B Round Registers 1 1 0 Filter A Limit Registers 1 1 1 Filter B Limit Registers The Filter A and B LF InterfacesTM are used to load data into the Filter A and B coefficient banks respectively. They are also used to load data into the configuration and control registers. The following section describes how the Filter A LF InterfaceTM works. The Filter A and B LF InterfacesTM are identical in function. If LDA and CFA11-0 are replaced with LDB and CFB11-0, the following section will describe how the Filter B LF InterfaceTM works. LDA is used to enable and disable the Filter A LF InterfaceTM. When LDA goes LOW, the Filter A LF InterfaceTM is enabled for data input. The first value fed into the interface on CFA11-0 is an address which determines what the interface is going to load. The three most significant bits (CFA11-9) determine if the LF InterfaceTM will load coefficient banks or Configuration/control registers (see Table 8). The nine least significant bits (CFA8-0) are the address for whatever is to be loaded (see Tables 9 through 14). For example, to load address 15 of the Filter A coefficient banks, the first data value into the LF InterfaceTM should be 00FH. Table 9 Fltr. A Round Regs. REGISTER ADDRESS (HEX) 0 800 1 801 Table 10 Fltr. A Select Regs REGISTER ADDRESS (HEX) 0 400 1 401 Table 11 Fltr. A Limit Regs. REGISTER ADDRESS (HEX) 0 C00 1 C01 14 80E 15 80F 14 40E 15 40F 14 C0E 15 C0F Table 12 Fltr. B Round Regs REGISTER ADDRESS (HEX) 0 A00 1 A01 Table 13 Fltr. B Select Regs REGISTER ADDRESS (HEX) 0 600 1 601 Table 14 Fltr. B Limit Regs REGISTER ADDRESS (HEX) 0 E00 1 E01 14 A0E 15 A0F 14 60E 15 60F 14 E0E 15 E0F LOGIC Devices Incorporated Video Imaging Products 11 Feb 5, 2003 LDS.3321-A 11 Page

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