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PDF W332M64V-XBX Data sheet ( Hoja de datos )

Número de pieza W332M64V-XBX
Descripción 32Mx64 Synchronous DRAM
Fabricantes White Electronic Designs 
Logotipo White Electronic Designs Logotipo



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No Preview Available ! W332M64V-XBX Hoja de datos, Descripción, Manual

White Electronic Designs
W332M64V-XBX
www.DataSheet4U.com
32Mx64 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm
3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 32M x 64
Weight: W332M64V-XBX - 2.5 grams typical
BENEFITS
41% SPACE SAVINGS
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Pinout compatible with lower densities
WEDPN4M64V-XBX, WEDPN8M64V-XBX and
WEDPN16M64V-XBX
* This product is subject to change without notice.
GENERAL DESCRIPTION
The 256MByte (2Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 134,217,728-bit banks is organized as 8,192
rows by 1,024 columns by 16 bits.
Read and write accesses to the SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 2Gb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows
the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging
one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 2Gb SDRAM is designed to operate at 3.3V. An auto
refresh mode is provided, along with a power-saving,
power-down mode.
February 2005
Rev. 0
Discrete Approach
11.9 11.9 11.9 11.9
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
Area
4 x 265mm2 = 1060mm2
1
ACTUAL SIZE
White Electronic Designs
W332M64V-XBX
25
25
S
A
V
I
N
G
S
625mm2
41%
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 page




W332M64V-XBX pdf
White Electronic Designs
W332M64V-XBX
www.DataSheet4U.com
FIGURE. 3 – MODE REGISTER DEFINITION
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Reserved* Reserved* WB Op Mode CAS Latency BT Burst Length
Mode Register (Mx)
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
0
1
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
--
- All other states reserved
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
TABLE 1 – BURST DEFINITION
Burst
Length
2
4
8
Full
Page
(y)
Starting Column
Address
A0
0
1
A1 A0
00
01
10
11
A2 A1 A0
000
001
010
011
100
101
110
111
n = A 0-9
(location 0-y)
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1 0-1
1-0 1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTES:
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-9 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
February 2005
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

5 Page





W332M64V-XBX arduino
White Electronic Designs
W332M64V-XBX
www.DataSheet4U.com
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
Parameter
Access time from CLK (pos. edge)
CL = 3
CL = 2
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time (22)
CL = 3
CL = 2
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3 (10)
CL = 2 (10)
Data-out low-impedance time
Data-out hold time (load) (26)
Data-out hold time (no load)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows) – Commercial, Industrial
Refresh period (8,192 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
WRITE recovery time
(23)
(24)
Exit SELF REFRESH to ACTIVE command
Symbol
-100
Min Max
-125
Min Max
-133
Min Max
tAC 7
6 5.5
tAC 7 6 6
tAH 1
1 0.8
tAS 2
2 1.5
tCH 3
3 2.5
tCL 3
3 2.5
tCK 10 8 7.5
tCK 13 10 10
tCKH 1
1 0.8
tCKS 2
2 1.5
tCMH 1
1 0.8
tCMS 2
2 1.5
tDH 1
1 0.8
tDS 2
2 1.5
tHZ 7
6 5.5
tHZ 7 6 6
tLZ 1 1 1
tOH 3 3 3
tOHN 1.8 1.8 1.8
tRAS 50 120,000 50 120,000 50 120,000
tRC 70 68 68
tRCD 20 20 20
tREF 64 64 64
tREF 16 16 16
tRFC 70 70 70
tRP 20 20 20
tRRD 20 20 20
tT 0.3 1.2 0.3 1.2 0.3 1.2
1 CLK + 7ns
tWR
15
1 CLK + 7ns
15
1 CLK + 7.5
15
tXSR 80 80 75
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
February 2005
Rev. 0
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

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