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PDF TEA5764HN Data sheet ( Hoja de datos )

Número de pieza TEA5764HN
Descripción FM radio + RDS
Fabricantes NXP Semiconductors 
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TEA5764HN
FM radio + RDS
Rev. 02 — 9 August 2005
www.DataSheet4U.com
Product data sheet
1. General description
The TEA5764HN is a single chip electronically tuned FM stereo radio with Radio Data
System (RDS) and Radio Broadcast Data System (RBDS) demodulator and RDS/RBDS
decoder for portable application with fully integrated IF selectivity and demodulation.
The radio is completely adjustment free and only requires a minimum of small and low
cost external components.
The radio can tune to the European, US and Japanese FM bands. It has a low power
consumption and can operate at a low supply voltage.
2. Features
s High sensitivity due to integrated low noise RF input amplifier
s FM mixer for conversion of the US/Europe (87.5 MHz to 108 MHz) and Japanese FM
band (76 MHz to 90 MHz) to IF
s Preset tuning to receive Japanese TV audio up to 108 MHz
s Auto search tuning, raster 100 kHz
s RF automatic gain control circuit
s LC tuner oscillator operating with low cost fixed chip inductors
s Fully integrated FM IF selectivity
s Fully integrated FM demodulator;
s no external discriminator
s Crystal oscillator at 32768 Hz, or external reference frequency at 32768 Hz
s PLL synthesizer tuning system
s IF counter; 7-bit output via the I2C-bus
s Level detector; 4-bit level information output via the I2C-bus
s Soft mute: signal dependent mute function
s Mono/stereo blend: gradual change from mono to stereo, depending on signal
s Adjustment-free stereo decoder
s Autonomous search tuning function
s Standby mode
s MPX output
s One software programmable port
s Fully integrated RDS/RBDS demodulator in accordance with EN50067
s RDS/RBDS decoder with memory for two RDS data blocks provides block
synchronization and error correction; block data and status information are available
via the I2C-bus
s Audio pause detector

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TEA5764HN pdf
Philips Semiconductors
7. Pinning information
7.1 Pinning
TEA5764HNwww.DataSheet4U.com
FM radio + RDS
terminal 1
index area
LOOPSW 1
CPOUT 2
LO1 3
LO2 4
CD1 5
PILLP 6
SWPORT 7
BUSENABLE 8
VREFDIG 9
SCL 10
TEA5764HN
30 GNDA
29 n.c.
28 GNDD
27 MPXIN
26 MPXOUT
25 VAFL
24 VAFR
23 TMUTE
22 INTCON1
21 n.c.
001aab459
Fig 2. Pin configuration
Transparent top view
7.2 Pin description
Table 3: Pin description
Symbol
Pin Description
LOOPSW
1
synthesizer PLL loop filter switch output
CPOUT
2 charge pump output of synthesizer PLL
LO1 3 local oscillator coil connection 1
LO2 4 local oscillator coil connection 2
CD1
5 VCO supply decoupling capacitor
PILLP
6 pilot PLL loop filter
SWPORT
7
software programmable port output
BUSENABLE 8
I2C-bus enable input
VREFDIG
9
digital reference voltage for I2C-bus signals
SCL
10 I2C-bus clock line input
SDA
11 I2C-bus data line input and output
n.c. 12 not connected
GNDD
13 digital ground
GNDD
14 digital ground
VCCD
15
CD2/INTCON3 16
digital supply voltage
internally connected
TEA5764HN_2
Product data sheet
Rev. 02 — 9 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 64

5 Page





TEA5764HN arduino
Philips Semiconductors
TEA5764HNwww.DataSheet4U.com
FM radio + RDS
8.19.2 RDS data and clock direct
The RDS demodulator retrieves the RDS data and clock signals, this data can be put
directly onto pins VAFL and VAFR by setting bit RDSCDA to logic 1.
8.19.2.1 RDS/RBDS decoder
The RDS decoder provides block synchronization, error correction and flywheel function
for reliable extraction of RDS or RBDS block data. Different modes of operation can be
selected to fit different application requirements. Availability of new data is signalled by bit
DAVFLG and output pin INTX which generates an interrupt. Up to two blocks of data and
status information are available via the I2C-bus in a single transmission.
The behavior of the DAVFLG is described in Section 10.
8.20 Audio pause detector
The audio pause detector monitors the audio modulation for pauses and responds to low
levels. The modulation threshold can be adjusted in 4 steps of 4 dB by control bits PL[1:0].
The minimum time for detecting a pause can be adjusted by control bits PT[1:0] as shown
in Table 38. When a pause occurs, flag PDFLAG is set to logic 1 and a hardware interrupt
is generated; see Section 9.1.4.6.
8.21 Auto search and Preset mode
In Search mode the TEA5764HN can search channels automatically; see Figure 3.
TEA5764HN_2
Product data sheet
Rev. 02 — 9 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 64

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