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PDF R2023K Data sheet ( Hoja de datos )
| Número de pieza | R2023K | |
| Descripción | 2-wire Serial Interface Real Time Clock IC | |
| Fabricantes | RICOH | |
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R2023K/T
www.DataSheet4U.com
2-wire Serial Interface Real Time Clock IC
OUTLINE
NO.EA-124-070221
The R2023K/T is a CMOS real-time clock IC connected to the CPU by two signal lines, SCL, SDA, and configured
to perform serial transmission of time and calendar data to the CPU. The periodic interrupt circuit is configured to
generate interrupt signals with six selectable interrupts ranging from 0.5 seconds to 1 month. The 2 alarm
interrupt circuits generate interrupt signals at preset times. As the oscillation circuit is driven under constant
voltage, fluctuation of the oscillator frequency due to supply voltage is small, and the time keeping current is small
(TYP. 0.45µA at 3V). The oscillation halt sensing circuit can be used to judge the validity of internal data in such
events as power-on; The supply voltage monitoring circuit is configured to record a drop in supply voltage below
two selectable supply voltage monitoring threshold settings. The 32.768kHz clock output function (CMOS output
with control pin) is intended to output sub-clock pulses for the external microcomputer. The oscillation adjustment
circuit is intended to adjust time counts with high precision by correcting deviations in the oscillation frequency of
the crystal oscillator. Since the package for these ICs are TSSOP10G (4.0x2.9x1.0: R2023T) or FFP12
(2.0x2.0x1.0: R2023K), high density mounting of ICs on boards is possible.
FEATURES
• Minimum Timekeeping supply voltage TYP:0.66 to 5.5v (Worst: 1.00V to 5.5v); VDD pin
• Low power consumption
0.45µA TYP at VDD=3V (1.00µA MAX.)
• Two signal lines (SCL, SDA) required for connection to the CPU.
• Time counters (counting hours, minutes, and seconds) and calendar counters (counting years, months, days,
and weeks) (in BCD format)
• Interrupt circuit configured to generate interrupt signals (with interrupts ranging from 0.5 seconds to 1 month) to
the CPU and provided with an interrupt flag and an interrupt halt
• 2 alarm interrupt circuits (Alarm_W for week, hour, and minute alarm settings and Alarm_D for hour and minute
alarm settings)
• With Power-on flag to prove that the power supply starts from 0V
• 32-kHz clock output pin (CMOS push-pull output with control pin)
• Supply voltage monitoring circuit with two supply voltage monitoring threshold settings
• Automatic identification of leap years up to the year 2099
• Selectable 12-hour and 24-hour mode settings
• High precision oscillation adjustment circuit
• Built-in oscillation stabilization capacitors (CG and CD)
• Package TSSOP10G (4.0mm x 2.9mm x 1.0mm: R2023T) FFP12 (2.0mm x 2.0mm x 1.0mm: R2023K)
• CMOS process
1
1 page  
R2023K/T
www.DataSheet4U.com
DC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified:
VSS=0V, VDD=3.0V, Topt=-40 to +85°C, Crystal oscillator 32768Hz,CL=7pF,R1=50kΩ)
Symbol
Item
Pin Name
Conditions
Min.
VIH
“H” Input Voltage
SCL, SDA, VDD=1.7 to 5.5V
0.8x
CLKC
VDD
VIL “L” Input Voltage
-0.3
IOH
IOL1
IOL2
IOL3
IIL
ICLKC
IOZ
IDD
VDETH
VDETL
“H” Output
Current
“L” Output
Current
Input Leakage
Current
Pull-down Resister
Input Leakage Current
Output Off-state
Current
Time Keeping Current
32KOUT
32KOUT
INTRA
INTRB
SDA
SCL
CLKC
SDA,
INTRA ,
INTRB
VDD
Supply Voltage
Monitoring Voltage
“H”
Supply Voltage
Monitoring Voltage “L”
VDD
VDD
VOH=VDD-0.5V
VOL=0.4V
0.5
2.0
VI=5.5V or VSS
VDD=5.5V
VI=5.5V
VO=5.5V or VSS
VDD=5.5V
3.0
-1.0
-1
VDD=3V,
SCL=SDA=CLKC=0V
32KOUT=OFF
OUTPUT=OPEN
CGout=CDout=0pF
*1)
Topt=-30 to +70°C
1.45
Topt=-30 to +70°C
1.15
Typ.
0.30
0.45
1.60
1.30
Max.
5.5
0.2x
VDD
-0.5
1.0
1.00
1
1.00
1.75
1.45
Unit
V
mA
mA
µA
µA
µA
µA
V
V
*1) For time keeping current when outputting 32.768kHz from the 32KOUT pin, see “P.45 TYPICAL
CHARACTERISTICS”. For time keeping current when CGOUT, CDOUT is not equal to 0pF, see “P.30
•Adjustment of oscillation frequency”.
5
5 Page 
Address Mapping
R2023K/T
www.DataSheet4U.com
Address
A3A2A1A0
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
A 1010
B 1011
C 1100
D 1101
E 1110
F 1111
Register Name
Second Counter
Minute Counter
Hour Counter
Day-of-week
Counter
Day-of-month
Counter
Month Counter and
Century Bit
Year Counter
Oscillation
Adjustment
Register *3)
Alarm_W
(Minute Register)
Alarm_W
(Hour Register)
Alarm_W
(Day-of-week
Register)
Alarm_D
(Minute Register)
Alarm_D
(Hour Register)
Control Register 1
*3)
Control Register 2
*3)
Data
D7 D6 D5 D4 D3 D2 D1 D0
- S40 S20 S10 S8 S4 S2 S1
*2)
- M40 M20 M10 M8 M4 M2 M1
- - H20 H10 H8 H4 H2 H1
P/ A
- - - - - W4 W2 W1
- - D20 D10 D8 D4 D2 D1
19 /20
Y80
DEV
*4)
-
Y40
F6
- MO10 MO8 MO4 MO2 MO1
Y20 Y10 Y8 Y4 Y2 Y1
F5 F4 F3 F2 F1 F0
- WM40 WM20 WM10 WM8 WM4 WM2 WM1
- - WH20 WH10 WH8 WH4 WH2 WH1
WP/ A
- WW6 WW5 WW4 WW3 WW2 WW1 WW0
- DM40 DM20 DM10 DM8 DM4 DM2 DM1
-
-
WALE
-
-
DALE
DH20
DP/ A
-
12 /24
DH10
-
CLEN2
DH8
-
TEST
DH4
-
CT2
DH2
-
CT1
DH1
-
CT0
VDSL VDET XST PON CLEN1 CTFG WAFG DAFG
*5)
Notes:
* 1) All the data listed above accept both reading and writing.
* 2) The data marked with "-" is invalid for writing and reset to 0 for reading.
* 3) When the PON bit is set to 1 in Control Register 2, all the bits are reset to 0 in Oscillation Adjustment
Register, Control Register 1 and Control Register 2 excluding the XST bit.
* 4) When DEV=0, the oscillation adjustment circuit is configured to allow correction of a time count gain or loss
up
to ±1.5ppm. When DEV=1, the oscillation adjustment circuit is configured to allow correction of a time count
gain or loss up to or ±0.5ppm.
* 5) PON is a power-on-reset flag.
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet R2023K.PDF ] | |
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